POWER10 adds some return-oriented programming (ROP) instructions and
this patch adds support for them. You will notice that they are enabled
for POWER8 and later, not just POWER10 and later. This is on purpose.
This allows the instructions to be added to POWER8 binaries that can be
run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these
instructions just act as nop's.
opcodes/
* ppc-opc.c (insert_dw, (extract_dw): New functions.
(DW, (XRC_MASK): Define.
(powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
gas/
* testsuite/gas/ppc/rop-checks.d,
* testsuite/gas/ppc/rop-checks.l,
* testsuite/gas/ppc/rop-checks.s,
* testsuite/gas/ppc/rop.d,
* testsuite/gas/ppc/rop.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
commit f478212851 did the regen by hand, missed a change in
ld/configure and didn't update line numbers. Fix that, and an old
regen of ld/Makefile.in with the wrong automake.
bfd/
* configure: Regenerate.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* Makefile.in: Regenerate.
* configure: Regenerate.
libctf/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
zlib/
* configure: Regenerate.
Add support for the pause hint instruction, as specified in the
Zihintpause extension. The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set). The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Added
INSN_CLASS_ZIHINTPAUSE.
* testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
the pause hint instruction.
* testsuite/gas/riscv/pause.s: Likewise.
include/
* opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
for pause hint instruction.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them. Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.
This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
(enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
frozen extensions.
opcodes/
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
These fail on tic30 due to that target using a different comment char.
* testsuite/gas/macros/app1.d: xfail tic30.
* testsuite/gas/macros/app2.d: Likewise.
* testsuite/gas/macros/app3.d: Likewise.
* testsuite/gas/macros/app4.d: Likewise.
RISC-V instruction/code is always little endian, but data might be
big-endian. Therefore, we can not use the original bfd_get/bfd_put
to get/put the code for big endian targets. Add new riscv_get_insn
and riscv_put_insn to always get/put code as little endian can resolve
the problem. Just remember to update them once we have supported
the 48-bit/128-bit instructions in the future patches.
bfd/
* config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and
riscvbe*-*-*. Also added riscv_elf[32|64]_be_vec.
* configure.ac: Handle riscv_elf[32|64]_be_vec.
* configure: Regenerate.
* elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for
riscv_is_insn_reloc.
(riscv_get_insn): RISC-V instructions are always little endian, but
bfd_get may be used for big-endian, so add new riscv_get_insn to handle
the insturctions.
(riscv_put_insn): Likewsie.
(riscv_is_insn_reloc): Check if we are relocaing an instruction.
(perform_relocation): Call riscv_is_insn_reloc to decide if we should
use riscv_[get|put]_insn or bfd_[get|put].
(riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32
or bfd_[get|put]l16 for code.
(riscv_elf_relocate_section): Likewise.
(riscv_elf_finish_dynamic_symbol): Likewise.
(riscv_elf_finish_dynamic_sections): Likewise.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_pc): Likewise.
(riscv_elf_object_p): Handled for big endian.
(TARGET_BIG_SYM, TARGET_BIG_NAME): Defined.
* targets.c: Add riscv_elf[32|64]_be_vec.
(_bfd_target_vector): Likewise.
gas/
* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
elf32-bigriscv.
(install_insn): Always write instructions as little endian.
(riscv_make_nops): Likewise.
(md_convert_frag_branch): Likewise.
(md_number_to_chars): Write data in target endianness.
(options, md_longopts): Add -mbig-endian and -mlittle-endian options.
(md_parse_option): Handle the endian options.
* config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
already defined.
* configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.
ld/
* configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
riscv32be*-*-linux*, and riscv64be*-*-linux*.
* Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and
eelf32briscv_ilp32.c.
* Makefile.in: Regenerate.
* emulparams/elf32briscv.sh: Added.
* emulparams/elf32briscv_ilp32.sh: Likewise.
* emulparams/elf32briscv_ilp32f.sh: Likewise.
* emulparams/elf64briscv.sh: Likewise.
* emulparams/elf64briscv_lp64.sh: Likewise.
* emulparams/elf64briscv_lp64f.sh: Likewise.
For non-relocatable link with SHF_LINK_ORDER inputs, allow mixed indirect
and data inputs with ordered and unordered inputs:
1. Add pattern to bfd_section for the matching section name pattern in
linker script and update BFD_FAKE_SECTION.
2. Sort the consecutive bfd_indirect_link_order sections with the same
pattern to allow linker script to overdide input section order.
3. Place unordered sections before ordered sections.
4. Change the offsets of the indirect input sections only.
bfd/
PR ld/26256
* elflink.c (compare_link_order): Place unordered sections before
ordered sections.
(elf_fixup_link_order): Add a link info argument. Allow mixed
ordered and unordered input sections for non-relocatable link.
Sort the consecutive bfd_indirect_link_order sections with the
same pattern. Change the offsets of the bfd_indirect_link_order
sections only.
(bfd_elf_final_link): Pass info to elf_fixup_link_order.
* section.c (bfd_section): Add pattern.
(BFD_FAKE_SECTION): Initialize pattern to NULL.
* bfd-in2.h: Regenerated.
gas/
PR ld/26256
* config/obj-elf.c (obj_elf_change_section): Also filter out
SHF_LINK_ORDER.
ld/
PR ld/26256
* ldlang.c (gc_section_callback): Set pattern.
* testsuite/ld-elf/pr26256-1.s: New file.
* testsuite/ld-elf/pr26256-1.t: Likewise.
* testsuite/ld-elf/pr26256-1a.d: Likewise.
* testsuite/ld-elf/pr26256-1b.d: Likewise.
* testsuite/ld-elf/pr26256-2.s: Likewise.
* testsuite/ld-elf/pr26256-2.t: Likewise.
* testsuite/ld-elf/pr26256-2a.d: Likewise.
* testsuite/ld-elf/pr26256-2b-alt.d: Likewise.
* testsuite/ld-elf/pr26256-2b.d: Likewise.
* testsuite/ld-elf/pr26256-3.s: Likewise.
* testsuite/ld-elf/pr26256-3a.d: Likewise.
* testsuite/ld-elf/pr26256-3a.t: Likewise.
* testsuite/ld-elf/pr26256-3b.d: Likewise.
* testsuite/ld-elf/pr26256-3b.t: Likewise.
This allows alignments up to 2**TC_ALIGN_LIMIT, which might be larger
than an unsigned int can hold.
PR 27101
* read.c (s_align): Use a large enough type for "align" to hold
the result of get_absolute_expression.
While "set $0, $0" works, that's not the documented instruction to do
nothing for MMIX. However, I'm not changing it for "nop_type 5" as
seen in gas.exp and org-1.s, because "set $0, $0" seems like it could
be re-used there, for some future ISA.
gas/
* config/tc-mmix.h (md_single_noop_insn): Change to "swym 0".
Update 80387 floating point 's' suffix to read:
* Integer constructors are '.word', '.long' or '.int', and '.quad'
for the 16-, 32-, and 64-bit integer formats. The corresponding
instruction mnemonic suffixes are 's' (short), 'l' (long), and 'q'
(quad).
instead of 's' (single).
PR gas/27106
* doc/c-i386.texi: Update 80387 floating point 's' suffix
This tidies initialisation of target common sections, doing so using a
static initialiser rather than via code and deleting unnecessary
symbol_ptr_ptr variables (the one in asection is used instead).
The patch also initialises ecoff.c:bfd_debug_section using
BFD_FAKE_SECTION. That does change bfd_debug_section slightly,
output_section was NULL now bfd_debug_section, and symbol_ptr_ptr
was NULL now &bfd_debug_section.symbol, but I believe those changes
are safe.
bfd/
* ecoff.c (bfd_debug_section): Init using BFD_FAKE_SECTION.
(ecoff_scom_section, ecoff_scom_symbol): Statically init using
BFD_FAKE_SECTION and GLOBAL_SYM_INIT. Delete initialisation code.
(ecoff_scom_symbol_ptr): Delete.
* elf32-m32r.c (m32r_elf_scom_section, m32r_elf_scom_symbol),
(m32r_elf_scom_symbol_ptr),
* elf32-score.c (score_elf_scom_section, score_elf_scom_symbol),
(score_elf_scom_symbol_ptr),
* elf32-score7.c (score_elf_scom_section, score_elf_scom_symbol),
(score_elf_scom_symbol_ptr),
* elf32-tic6x.c (tic6x_elf_scom_section, tic6x_elf_scom_symbol),
(tic6x_elf_scom_symbol_ptr),
* elf32-v850.c (v850_elf_scom_section, v850_elf_scom_symbol),
(v850_elf_scom_symbol_ptr),
(v850_elf_tcom_section, v850_elf_tcom_symbol),
(v850_elf_tcom_symbol_ptr),
(v850_elf_zcom_section, v850_elf_zcom_symbol),
(v850_elf_zcom_symbol_ptr),
* elf64-mmix.c (mmix_elf_reg_section, mmix_elf_reg_section_symbol),
(mmix_elf_reg_section_symbol_ptr),
* elfxx-mips.c (mips_elf_scom_section, mips_elf_scom_symbol),
(mips_elf_scom_symbol_ptr): Likewise.
gas/
* ecoff.c (ecoff_frob_symbol): Rename scom_section to
ecoff_scom_section and statically initialise.
elfNN_bed was made writable as an expedient means of communicating
ld -z max-page-size and ld -z common-page-size values to BFD linker
code, and even for objcopy to communicate segment alignment between
copy_private_bfd_data, rewrite_elf_program_header and
assign_file_positions_for_load_sections. Some time later elfNN_bed
elf_osabi was written by gas. It turns out none of these
modifications to elfNN_bed was necessary, so make it const again.
include/
* bfdlink.h (struct bfd_link_info): Add maxpagesize and
commonpagesize.
bfd/
* elfxx-target.h (elfNN_bed): Constify.
* bfd.c (bfd_elf_set_pagesize): Delete.
(bfd_emul_set_maxpagesize, bfd_emul_set_commonpagesize): Delete.
* elf.c (get_program_header_size): Get commonpagesize from
link info.
(_bfd_elf_map_sections_to_segments): Get maxpagesize from link info.
(assign_file_positions_for_load_sections): Likewise.
(assign_file_positions_for_non_load_sections): Likewise.
(rewrite_elf_program_header): Add maxpagesize param. Set map_p_align.
(copy_private_bfd_data): Don't call bfd_elf_set_maxpagesize.
Instead pass maxpagesize to rewrite_elf_program_header.
* elf32-nds32.c (relax_range_measurement): Add link_info param.
Get maxpagesize from link_info. Adjust caller.
* bfd-in2.h: Regenerate.
gas/
* config/obj-elf.c (obj_elf_section): Don't set elf_osabi here.
(obj_elf_type): Likewise.
ld/
* ld.h (ld_config_type): Delete maxpagesize and commonpagesize.
* emultempl/elf.em: Use link_info rather than config
for maxpagesize and commonpagesize.
* emultempl/ppc32elf.em: Likewise.
* ldexp.c (fold_binary, fold_name): Likewise.
* ldemul.c (after_parse_default): Likewise.
(set_output_arch_default): Don't call bfd_emul_set_maxpagesize
or bfd_emul_set_commonpagesize.
rx-elf is an odd target with non-standard names for default text, data
and bss sections. This patch tweaks a new test to make it pass.
* testsuite/gas/elf/section27.s: Reorder .text, .data and .bss
so that output section order does not depend on those sections
being already created. Use ".section .text" rather than ".text".
I've made all labels normal labels so that there's no confusion between
the different targets which is which and I match them in the .d files
with .* as Alan suggested.
Hex offsets I match with [0-9a-fx]+ since some targets prefix them with
0x, some don't, etc.
* testsuite/gas/i386/align-branch-9.s: Don't use labels that are
automatically local for ELF targets.
* testsuite/gas/i386/branch.s: Likewise.
* testsuite/gas/i386/x86-64-align-branch-9.s: Likewise.
* testsuite/gas/i386/x86-64-branch.s: Likewise.
* testsuite/gas/i386/align-branch-9.d: Adjust to match more targets.
* testsuite/gas/i386/branch.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-9.d: Likewise.
* testsuite/gas/i386/x86-64-branch.d: Likewise.
https://github.com/riscv/riscv-asm-manual/pull/61
We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
and zext.w. In a certain sense, zext.b is not a pseudo - It is an
alias of andi. Similarly, sext.b and sext.h are aliases of other
rvb instructions, when we enable b extension; But they are pseudos
when we just enable rvi. However, this patch does not consider the
rvb cases. Besides, zext.w is only valid in rv64.
gas/
* config/tc-riscv.c (riscv_ext): New function. Use md_assemblef
to expand the zext and sext pseudos, to give them a chance to be
expanded into c-ext instructions.
(macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
* testsuite/gas/riscv/ext.s: New testcase.
* testsuite/gas/riscv/ext-32.d: Likewise.
* testsuite/gas/riscv/ext-64.d: Likewise.
include/
* opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
opcodes/
* riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
bfd/
* elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return
TRUE if we don't care the versions of the extensions. These extensions
are added to the subset list for special purposes, with the explicit
versions or the RISCV_UNKNOWN_VERSION versions.
(riscv_parse_add_subset): If we do care the versions of the extension,
and the versions are unknown, then report errors for the non-implicit
extensions, and return directly for the implicit one.
(riscv_arch_str1): Do not output i extension after e, and the extensions
which versions are unknown.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
and INSN_CLASS_ZIFENCEI.
* testsuite/gas/riscv/march-imply-i.s: New testcase.
* testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version
of i is less than 2.1, and zi* are supported in the chosen spec, so
enable the fence.i and csr instructions, also output the implicit zi* to
the arch string.
* testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
not supported in the spec 2.2. Enable the related instructions since
i's version is less than 2.1, but do not output them.
* testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version
of i is 2.1, so don't add it's implicit zi*, and disable the related
instructions.
* testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
explicitly, so enable the related instructions.
* testsuite/gas/riscv/march-imply-i2p0.d: Removed.
* testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
* opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
* riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
zifencei and zicsr.
For
.globl foo2
.section .data.foo,"aR"
.align 4
.type foo2, @object
.size foo2, 4
foo2:
.long 2
.globl foo1
.section .data.foo
.align 4
.type foo1, @object
.size foo1, 4
foo1:
.long 1
generate a new section if the SHF_GNU_RETAIN bit doesn't match.
* config/obj-elf.c (SEC_ASSEMBLER_SHF_MASK): New.
(get_section_by_match): Also check if SEC_ASSEMBLER_SHF_MASK of
sh_flags matches. Rename info to sh_info.
(obj_elf_change_section): Don't check previous SHF_GNU_RETAIN.
Rename info to sh_info.
(obj_elf_section): Rename info to sh_info. Set sh_flags for
SHF_GNU_RETAIN.
* config/obj-elf.h (elf_section_match): Rename info to sh_info.
Add sh_flags.
* testsuite/gas/elf/elf.exp: Run section27.
* testsuite/gas/elf/section24b.d: Updated.
* testsuite/gas/elf/section27.d: New file.
* testsuite/gas/elf/section27.s: Likewise.
These two extended mnemonics are documented in the Principles of
Operations manual but currently not supported by Binutils. They
provide aliases for already supported instructions with the zero flag
being set. The flag otherwise is mingled into one of the immediate
operands what makes asm code much harder to read.
opcodes/
* s390-opc.txt: Add risbgz and risbgnz.
* s390-opc.c (U6_26): New operand type.
(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
mask.
gas/
* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
Add extended mnemonics used in the HLASM assembler. All of them are
just aliases for instructions we already support and help when
assembling code which was written for the HLASM assembler.
The HLASM mnemonics are documented here:
https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf
See the 'Branching with extended mnemonic codes' chapter.
objdump will still print the existing mnemonics with the exception of
relative nop branches (i.e. conditional branches with an empty
condition code mask). Now we have jnop and jgnop which will be used
by objdump when possible.
The same change have been applied to the LLVM assembler:
https://reviews.llvm.org/D92185
opcodes/
* s390-opc.txt: Add extended mnemonics.
gas/
* testsuite/gas/s390/esa-g5.s: Test new extended mnemonics.
* testsuite/gas/s390/esa-g5.d: Likewise.
* testsuite/gas/s390/esa-z900.s: Likewise.
* testsuite/gas/s390/esa-z900.d: Likewise.
* testsuite/gas/s390/zarch-z900.s: Likewise.
* testsuite/gas/s390/zarch-z900.d: Likewise.
ld/
* testsuite/ld-s390/tlsbin_64.dd: The newly added jgnop mnemonic
replaces long relative branches with empty condition code mask.
G is a special case, consider the ISA spec github issue as follows,
https://github.com/riscv/riscv-isa-manual/issues/575
My understand is that - i, m, a, f and d extensions are not g's implicit
extensions, they are g's expansions. The zifencei is the implicit extension
of g, and so is zicsr, since it is implicited by f (or i2p1). However,
we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
will not output to the arch string, it is only used to check what implicit
extensions are need to be added.
bfd/
* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
RISCV_UNKNOWN_VERSION versions.
(riscv_parse_std_ext): Add g to the subset list, we only use it
to add the implicit extensions, but won't output it to arch string.
(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
for g extension.
(riscv_arch_str1): Do not output g to the arch string.
* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.
gas/
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
are not supported in the ISA spec v2.2, so don't add and output them.
include/
* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions. That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions. For now we
follow the following rules to add the implicit extensions,
* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.
Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.
bfd/
* elfnn-riscv.c (riscv_merge_std_ext): Updated since
riscv_lookup_subset is changed.
* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
extensions' order quickly.
(riscv_init_ext_order): New function. Init the riscv_ext_order
according to the riscv_supported_std_ext and parse_config[i].class
automatically.
(riscv_compare_subsets): New function. Similar to the strcmp, but
compare the subsets with the specific order.
(riscv_lookup_subset): Return TRUE and set `current` to the subset
if it is found. Otherwise, return FALSE and set `current` to the
place where we should insert the subset.
(riscv_add_implicit_subset): New function. Search the list first,
and then find the right place to add the implicit_subset.
(riscv_parse_add_subset): Since We have to add all arch string
extensions first, and then start to add their implicit extensions.
We can add arch string extensions in order by the original
riscv_add_subset, and then add the implicit subsets by the
riscv_add_implicit_subset. Besides, do not add the implicit
extensions if we failed to find their default versions.
(riscv_parse_std_ext): Updated.
(riscv_parse_add_implicit_subsets): New function. Add all implicit
extensions according to the arch string extensions.
(riscv_parse_subset): Call riscv_init_ext_order and
riscv_parse_add_implicit_subsets, before and after parsing the
arch string. Remove parts of the ISA conflict checking since
the implicit extensions are added.
* elfxx-riscv.h (riscv_lookup_subset): Updated.
gas/
* config/tc-riscv.c (riscv_subset_supports): Updated.
* testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to
add the implicit zicsr and zifencei when i's version less than 2.1.
* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
* testsuite/gas/riscv/march-imply-d.d: Likewise.
* testsuite/gas/riscv/march-imply-f.d: Likewise.
* testsuite/gas/riscv/march-imply-q.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
Keep the riscv_add_subset to do the same thing, and use a new
function, riscv_parse_add_subset, to cover most of the things
when parsing, including find the default versions for extensions,
and check whether the versions are valid. The version 0p0 should
be an invalid version, that is the mistake I made before. This
patch clarify the version rules as follows,
* We accept any version of extensions set by users, except 0p0.
* The non-standard x extensions must be set with versions in arch string.
* If user don't set the versions, or set 0p0 for the extensions, then try
to find the supported versions according to the chosen ISA spec.
Otherwise, report errors rather than output 0p0 for them.
Besides, we use as_bad rather than as_fatal to report more errors
for assembler.
bfd/
* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
(riscv_add_subset): Likewise.
(riscv_release_subset_list): Likewise.
(riscv_parse_add_subset): New function. Find and check the
versions before adding them by riscv_add_subset.
(riscv_parsing_subset_version): Remove use_default_version
and change the version type from unsigned to int. Set the
versions to RISCV_UNKNOWN_VERSION if we can not find them
in the arch string.
(riscv_parse_std_ext): Updated.
(riscv_parse_prefixed_ext): Updated. Since we use as_bad
rather than as_fatal to report more errors, return NULL
string if the parsed end_of_version is NULL, too.
(riscv_parse_subset): Use a new boolean, no_conflict, to
report more errors when we have more than one ISA conflicts.
* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
RISCV_UNKNOWN_VERSION.
(riscv_lookup_subset_version): Removed.
(riscv_parse_subset_t): Updated.
gas/
* config/tc-riscv.c (riscv_get_default_ext_version):
Change the version type from unsigned to int.
(riscv_set_arch): Use as_bad rather than as_fatal to
report more errors.
* testsuite/gas/riscv/attribute-02.d: Updated since x must be
set with versions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
in the spec 2.2, so choose the newer spec.
* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-porder.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.
include/
* opcode/riscv.h (riscv_ext_version):
Change the version type from unsigned to int.
Although I cannot find any RISC-V specs said that uppercases are not
allowed in the arhc string, but seems like it is an established fact
both for GNU and LLVM. Therefore, we shouldn't allow the uppercases
for the non-standard x extensions, too.
bfd/
* elfxx-riscv.c (riscv_parse_subset): ISA string cannot contain
any uppercase letter.
gas/
* testsuite/gas/riscv/march-fail-uppercase-base.d: Updated.
* testsuite/gas/riscv/march-fail-uppercase.l: Updated.
* testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase.
Re-indent the related codes, unify and improve the related error messages
and comments. Besies, also re-write the testcases to cover more cases.
bfd/
* elfxx-riscv.c: Re-indent codes, unify and improve the error
messages and comments.
(riscv_parse_prefixed_ext): Stop parsing the prefixed class
extensions if the class is RV_ISA_CLASS_UNKNOWN, I get internal
errors before adding this check for march-fail-porder* testcases.
(riscv_parse_subset): Move the rv32 with q checking in front.
* elfxx-riscv.h: Likewise.
gas/
(These are new testcases that cover more cases)
* testsuite/gas/riscv/march-fail-base-01.d: The first extension must
be e, i or g.
* testsuite/gas/riscv/march-fail-base-01.l: Likewise.
* testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA.
* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
* testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard
extensions.
* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed
x extensions.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when
standard and prefixed extensions are set at the same time.
* testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise.
* testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise.
* testsuite/gas/riscv/march-fail-porder.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char-s.d: Only standard
extensions can use single char.
* testsuite/gas/riscv/march-fail-single-char-x.d: Likewise.
* testsuite/gas/riscv/march-fail-single-char-z.d: Likewise.
* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-s.d: All extensions
should be known, except the non-standard x extensions.
* testsuite/gas/riscv/march-fail-unknown-std.d: Likewise.
* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-z.d: Likewise.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
* testsuite/gas/riscv/march-fail-uppercase-base.d: Do not
allow any uppercase in the arch string.
* testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise.
* testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise.
* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
* testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions.
* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ef.l: Updated.
* testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext.
* testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
(The following testcases are removed and covered by new testcases)
* testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base.
* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std.
* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std.
* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x.
* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std.
* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std.
* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02.
* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
* testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-s-with-version.l: Likewise.
* testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-s.l: Likewise.
* testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
The previous change
"x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode"
to ignore segment override prefixes in 64-bit mode lead to dumping
branch hints as excessive prefixes:
ffffffff8109d5a0 <vmx_get_rflags>:
...
ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e>
^^^^^
In this particular case, those prefixes are not excessive but are used
to provide branch hints - taken/not-taken - to the CPU.
Assign active_seg_prefix in that particular case to consume them.
gas/
2002-11-29 Borislav Petkov <bp@suse.de>
* testsuite/gas/i386/branch.d: Add new branch insns test.
* testsuite/gas/i386/branch.s: Likewise.
* testsuite/gas/i386/i386.exp: Insert the new branch test.
* testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns.
* testsuite/gas/i386/x86-64-branch.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
opcodes/
2020-11-28 Borislav Petkov <bp@suse.de>
* i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
The ".persistent" section is for data that should be initialized during
load, but not during application reset.
The ".noinit" section is for data that should not be initialized during
load or application reset.
Targets utilizing the elf.sc linker script template can define
HAVE_{NOINIT,PERSISTENT}=yes to include the .noinit or .persistent
output sections in the generated linker script.
Targets with existing support for .noinit did not handle unique
.noinit.* and .gnu.linkonce.n.* sections the .noinit output section,
this patch also fixes that.
bfd/ChangeLog:
* elf.c (special_sections_g): Add .gnu.linkonce.n and .gnu.linkonce.p.
(special_sections_n): Add .noinit.
(special_sections_p): Add .persistent.
binutils/ChangeLog:
* testsuite/lib/binutils-common.exp (supports_noinit_section): New.
(supports_persistent_section): New.
gas/ChangeLog:
* testsuite/gas/elf/elf.exp: Run new tests.
* testsuite/gas/elf/section25.d: New test.
* testsuite/gas/elf/section25.s: New test.
* testsuite/gas/elf/section26.d: New test.
* testsuite/gas/elf/section26.s: New test.
ld/ChangeLog:
* emulparams/armelf.sh (OTHER_SECTIONS): Remove .noinit section
definition.
Define HAVE_{NOINIT,PERSISTENT}=yes.
* scripttempl/avr.sc (.noinit): Add .noinit.* and .gnu.linkonce.n.*
input section wildcard patterns.
* scripttempl/elf.sc: Define .noinit and .persistent sections when
HAVE_NOINIT or HAVE_PERSISTENT are defined to "yes".
* scripttempl/elf32msp430.sc (.noinit): Add .noinit.* and
.gnu.linkonce.n.*. input section wildcard patterns.
(.persistent): Add .persistent.* and
.gnu.linkonce.p.*. input section wildcard patterns.
* scripttempl/elfarcv2.sc (.noinit): Add .noinit.* and
.gnu.linkonce.n.*. input section wildcard patterns.
* scripttempl/pru.sc: Likewise.
* testsuite/ld-elf/noinit-sections-1.d: New test.
* testsuite/ld-elf/noinit-sections-2.d: New test.
* testsuite/ld-elf/noinit-sections-2.l: New test.
* testsuite/ld-elf/noinit-sections.s: New test.
* testsuite/ld-elf/persistent-sections-1.d: New test.
* testsuite/ld-elf/persistent-sections-2.d: New test.
* testsuite/ld-elf/persistent-sections-2.l: New test.
* testsuite/ld-elf/persistent-sections.s: New test.
Seen on arm-elf, where ELFOSABI_ARM is set too late to get a warning
when processing ifunc related directives on their source line.
../gas/as-new ifunc.s -o tmpdir/ifunc.o
../gas/as-new: symbol type STT_GNU_IFUNC is supported only by GNU and FreeBSD targets
ifunc.s: Assembler messages:
ifunc.s: Fatal error: can't close tmpdir/ifunc.o: sorry, cannot handle this file
This patch doesn't fix the real underlying problem, just the late
error message where "can't close" is a misdirection in this case.
* output-file.c (output_file_close): Remove "can't close" from
error message.
* testsuite/gas/mips/reginfo-2.l: Update expected output.
The SHF_GNU_RETAIN section flag is an extension to the GNU ELF OSABI.
It is defined as follows:
=========================================================
Section Attribute Flags
+-------------------------------------+
| Name | Value |
+-------------------------------------+
| SHF_GNU_RETAIN | 0x200000 (1 << 21) |
+-------------------------------------+
SHF_GNU_RETAIN
The link editor should not garbage collect the section.
=========================================================
The .section directive accepts the "R" flag, which indicates
SHF_GNU_RETAIN should be applied to the section.
There is not a direct mapping of SHF_GNU_RETAIN to the BFD
section flag SEC_KEEP. Keeping these flags distinct allows
SHF_GNU_RETAIN sections to be explicitly removed by placing them in
/DISCARD/.
bfd/ChangeLog:
* elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_retain.
(struct elf_obj_tdata): Increase has_gnu_osabi to 4 bits.
* elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_retain
for SHF_GNU_RETAIN.
(_bfd_elf_final_write_processing): Report if SHF_GNU_RETAIN is
not supported by the OSABI.
Adjust error messages.
* elflink.c (elf_link_input_bfd): Copy enabled has_gnu_osabi bits from
input BFD to output BFD.
(bfd_elf_gc_sections): gc_mark the section if SHF_GNU_RETAIN is set.
binutils/ChangeLog:
* NEWS: Announce SHF_GNU_RETAIN support.
* readelf.c (get_elf_section_flags): Handle SHF_GNU_RETAIN.
Recognize SHF_GNU_RETAIN and SHF_GNU_MBIND only for supported OSABIs.
* testsuite/binutils-all/readelf.exp: Run new tests.
Don't run run_dump_test when there isn't an assembler available.
* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Adjust
comment.
* testsuite/binutils-all/readelf-maskos-1a.d: New test.
* testsuite/binutils-all/readelf-maskos-1b.d: New test.
* testsuite/binutils-all/readelf-maskos.s: New test.
* testsuite/binutils-all/retain1.s: New test.
* testsuite/binutils-all/retain1a.d: New test.
* testsuite/binutils-all/retain1b.d: New test.
gas/ChangeLog:
* NEWS: Announce SHF_GNU_RETAIN support.
* config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit
between section declarations.
(obj_elf_parse_section_letters): Handle 'R' flag.
Handle numeric flag values within the SHF_MASKOS range.
(obj_elf_section): Validate SHF_GNU_RETAIN usage.
* doc/as.texi: Document 'R' flag to .section directive.
* testsuite/gas/elf/elf.exp: Run new tests.
* testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section22.d: New test.
* testsuite/gas/elf/section22.s: New test.
* testsuite/gas/elf/section23.s: New test.
* testsuite/gas/elf/section23a.d: New test.
* testsuite/gas/elf/section23b.d: New test.
* testsuite/gas/elf/section23b.err: New test.
* testsuite/gas/elf/section24.l: New test.
* testsuite/gas/elf/section24.s: New test.
* testsuite/gas/elf/section24a.d: New test.
* testsuite/gas/elf/section24b.d: New test.
include/ChangeLog:
* elf/common.h (SHF_GNU_RETAIN): Define.
ld/ChangeLog:
* NEWS: Announce support for SHF_GNU_RETAIN.
* ld.texi (garbage collection): Document SHF_GNU_RETAIN.
(Output Section Discarding): Likewise.
* testsuite/ld-elf/elf.exp: Run new tests.
* testsuite/ld-elf/retain1.s: New test.
* testsuite/ld-elf/retain1a.d: New test.
* testsuite/ld-elf/retain1b.d: New test.
* testsuite/ld-elf/retain2.d: New test.
* testsuite/ld-elf/retain2.ld: New test.
* testsuite/ld-elf/retain2.map: New test.
* testsuite/ld-elf/retain3.d: New test.
* testsuite/ld-elf/retain3.s: New test.
* testsuite/ld-elf/retain4.d: New test.
* testsuite/ld-elf/retain4.s: New test.
* testsuite/ld-elf/retain5.d: New test.
* testsuite/ld-elf/retain5.map: New test.
* testsuite/ld-elf/retain5lib.s: New test.
* testsuite/ld-elf/retain5main.s: New test.
* testsuite/ld-elf/retain6a.d: New test.
* testsuite/ld-elf/retain6b.d: New test.
* testsuite/ld-elf/retain6lib.s: New test.
* testsuite/ld-elf/retain6main.s: New test.
* read.c (stringer): Treat space separated, quote enclosed strings
as a single string.
* doc/as.texi (asciz): Mention this behaviour in the description
of the asciz directive.
* testsuite/gas/all/asciz.s: New test.
* testsuite/gas/all/asciz.d: New test driver.
* testsuite/gas/all/gas.exp: Run the new test.
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A.
Please note that FLAGM stays a Armv8.4-A feature but now can be
assigned to other architectures or CPUs.
New -march option +flagm is added to enable independently this
feature.
This patch fixes a mistake when enabling MVE instructions that disabled support
for single precision vmla and vmul for arm mode.
gas/ChangeLog:
2020-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 26858
* config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT.
* testsuite/gas/arm/pr26858.s: New test.
* testsuite/gas/arm/pr26858.d: New test.
The redundant -md option was removed in e4ae357fe8, but it is required
for backwards compatibility with GCC 10, which passes it to the
assembler implicitly in certain situations.
It is now silently ignored.
gas/ChangeLog:
* config/tc-msp430.c (OPTION_MOVE_DATA): Define.
(md_parse_option): Ignore OPTION_MOVE_DATA.
(md_longopts): Handle -md option.
* testsuite/gas/msp430/msp430.exp: Run new test.
* testsuite/gas/msp430/empty.s: New test.
* testsuite/gas/msp430/ignore-md.d: New test.
PR 26850
* dwarf2dbg.c (dwarf2_gen_line_info_1): Do not record lines in
sections that are not executable or not loadable.
(out_debug_line): Move warning message into dwarf2_gen_line_info_1.
* testsuite/gas/elf/dwarf2-20.s: New test.
* testsuite/gas/elf/dwarf2-20.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/warn-2.s: Use the .nop directive.
include * opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
This patch:
+ Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0].
+ Adds LS64 instruction tests.
+ Update LS64 feature test with new register.
+ Fix comment for AARCH64_OPND_Rt_LS64.
[0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):
if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
This patch adds check if Rt fulfills above requirement.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Originally, if the -mabi option isn't set, then assembler will set the
abi according to the architecture string in the riscv_after_parse_args.
But we should also check and reset the abi later since the architecture
string may be reset by the elf attributes. Therefore, set the abi to
the elf_flags in the riscv_after_parse_args seems too early. Besides,
we have to set the abi_xlen before assembling any instruction, so it
should be safe to call riscv_set_abi_by_arch at the place that we set
start_assemble to TRUE. However, one minor case is that we won't call
the md_assemble when we are assembling an file without any instruction.
It seems that we still need to set the abi in riscv_elf_final_processing,
to make sure that abi can be updated according to the elf arch attributes.
For the rv32i and most elf toolchains, this patch can fix the mis-matched
ABI errors for Run pr26391-5 and Run pr26391-6 testcases. Besides, it
also correct the elf header flags of the output objects. Consider the
new testcases, mabi-fail-02 and mabi-noabi-attr-[01|02|03], they are
failed before applying this patch.
But I still get the mis-matched ABI errors for the following toolchains
when runnung the riscv-gnu-toolchain regressions,
newlib-rv32imafc-ilp32f-[medlow|medany]
linux-rv32imac-ilp32-[medlow|medany]
linux-rv32imafdc-ilp32-[medlow|medany}
linux-rv64imac-lp64-[medlow|medany]
linux-rv64imafdc-lp64-[medlow|medany}
For the newlib-rv32imafc-ilp32f, although we try to choose the abi
according to the elf attributes, we will use FLOAT_ABI_SOFT rather
than the FLOAT_ABI_SINGLE for the assmebly file wihtout setting the
-mabi, but compiler will set the abi to FLOAT_ABI_SINGLE for the
C files.
As for the linux toolchains, we also get fails for Run pr26391-5 and
Run pr26391-6 testcases. Since the linux toolchain won't generate elf
attributes to correct the ISA, and the --with-arch configure option
isn't set, assembler will try to set the default arch to rv[32|64]g,
which means the FLOAT_ABI_DOUBLE will be choosed, and may be conflict
with the abi set by the toolchain.
Therefore, I would suggest that it's is more safe to set the --with-arch
when building binutils, but it may break some testcases. For example,
ld-scripts/fill and ld-scripts/empty-address-2 may be broken when c-ext
is set. We might insert R_RISCV_ALIGN to make sure the 4-byte alignment,
but the dump result will be a bit different from what the testcase expected.
However, this patch only fix the problem - the abi, elf_flags and the
instruction, which is generated according to the abi_xlen, are all fixed
once the elf attributes are set for most elf toolchains. Other mis-matched
ABI problems should be fixed when we always build the binutils with the
--with-arch= configure option.
gas/
* config/tc-riscv.c (explicit_mabi): New boolean to indicate if
the -mabi= option is explictly set.
(md_parse_option): Set explicit_mabi to TRUE if -mabi is set.
(riscv_set_abi_by_arch): New function. If the -mabi option isn't
set, then we set the abi according to the architecture string.
Otherwise, check if there are conflicts between architecture
and abi setting.
(riscv_after_parse_args): Move the abi setting to md_assemble nad
riscv_elf_final_processing.
(md_assemble): Call the riscv_set_abi_by_arch when we set the
start_assemble to TRUE.
(riscv_elf_final_processing): Likewise, in case the file without
any instruction.
* testsuite/gas/riscv/mabi-attr-01.s: New testcase.
* testsuite/gas/riscv/mabi-attr-02.s: Likewise.
* testsuite/gas/riscv/mabi-attr-03.s: Likewise.
* testsuite/gas/riscv/mabi-fail-01.d: Likewise.
* testsuite/gas/riscv/mabi-fail-01.l: Likewise.
* testsuite/gas/riscv/mabi-fail-02.d: Likewise.
* testsuite/gas/riscv/mabi-fail-02.l: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-01a.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-01b.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-02a.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-02b.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-03a.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-attr-03b.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-march-01.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-march-02.d: Likewise.
* testsuite/gas/riscv/mabi-noabi-march-03.d: Likewise.
This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.
Please note that early Armv8-A architectures do not officially support RAS
extension.
Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.
The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.
RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.
For details see [0].
[0] https://developer.arm.com/docs/ddi0595/i/
Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.
This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Symbol value is in bytes while fragS::fr_address is in octets. Fixes GAS
symver12 and symver13 tests on ELF targets with with OCTETS_PER_BYTE>1.
* config/obj-elf (elf_frob_symbol): Fix symbol value calculation
for versioned symbol aliases.
Signed-off-by: Christian Eggers <ceggers@gmx.de>
This patch adds new to Armv8.7 WFIT instruction which take one operand:
WFIT <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 570 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: Update test with WFIT insn.
* testsuite/gas/aarch64/system-5.s: Update test with WFIT insn.
opcodes/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch fixes errors with DSB instruction after introduction of DSB nXS
variant. That change would cause GAS to reject valid DSB immediate string
operands.
gas/ChangeLog:
2020-10-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB
immediate string operand.
* testsuite/gas/aarch64/system-4.d: Update test.
* testsuite/gas/aarch64/system-4.s: Update test.
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds new to Armv8.7 WFET instruction which take one operand:
WFET <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFET (Wait For Event with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 565 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: New test.
* testsuite/gas/aarch64/system-5.s: New test.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
and operand description.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.
DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:
DSB SYnXS|#28
DSB ISHnXS|#24
DSB NSHnXS|#20
DSB OSHnXS|#16
Please note that till now, for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:
CRm<3:2> #imm
00 16
01 20
10 24
11 28
This patch extends current AArch64 barrier instructions with above mapping.
Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.
For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (parse_operands): Add
AARCH64_OPND_BARRIER_DSB_NXS handler.
(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
aarch64_barrier_opt_hsh hash.
* testsuite/gas/aarch64/system-4-invalid.d: New test.
* testsuite/gas/aarch64/system-4-invalid.l: New test.
* testsuite/gas/aarch64/system-4-invalid.s: New test.
* testsuite/gas/aarch64/system-4.d: New test.
* testsuite/gas/aarch64/system-4.s: New test.
include/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_BARRIER_DSB_NXS.
(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.
opcodes/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
ins_barrier_dsb_nx.
* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
ext_barrier_dsb_nx.
* aarch64-opc.c (aarch64_print_operand): New options table
aarch64_barrier_dsb_nxs_options.
* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
Armv8.7-a instruction.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds support for AArch64 -march=armv8.7-a command line option
in GAS.
Please note that this change ONLY extends -march= command line interface
with a new "armv8.7-a" option. Architectural changes like new instructions
will be added in following patches.
gas/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (armv8.7-a): New arch.
* doc/c-aarch64.texi (-march=armv8.7-a): Update docs.
include/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
(AARCH64_ARCH_V8_7): New arch feature set.
opcodes/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (ARMV8_7): New macro.
Since a file slot is auto-assigned for the #APP marker appeared before
the first .file <NUMBER> directive has been seen, clear all auto-assigned
file slots when seeing the first .file <NUMBER> directive.
PR gas/26778
* * dwarf2dbg.c (num_of_auto_assigned): New.
(allocate_filenum): Increment num_of_auto_assigned.
(dwarf2_directive_filename): Clear the slots auto-assigned
before the first .file <NUMBER> directive was seen.
* testsuite/gas/i386/dwarf4-line-1.d: New file.
* testsuite/gas/i386/dwarf4-line-1.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf4-line-1.
gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
This patch introduces BRBE (Branch Record Buffer Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/brbe-invalid.d: New test.
* testsuite/gas/aarch64/brbe-invalid.l: New test.
* testsuite/gas/aarch64/brbe-invalid.s: New test.
* testsuite/gas/aarch64/brbe.d: New test.
* testsuite/gas/aarch64/brbe.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add BRBE system registers.
This patch introduces CSRE (Call Stack Recorder Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size
of a Call stack record) instruction. This instruction will be added in
a following, separate patch. This change only adds CSRE system
registers.
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/csre-invalid.d: New test.
* testsuite/gas/aarch64/csre-invalid.l: New test.
* testsuite/gas/aarch64/csre-invalid.s: New test.
* testsuite/gas/aarch64/csre.d: New test.
* testsuite/gas/aarch64/csre.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: New CSRE system registers defined.
bfd * po/es.po: Fix printf format
binutils * windmc.c: Fix printf format
gas * config/tc-arc.c: Fix printf format
opcodes * po/es.po: Fix printf format
sim * arm/armos.c: Fix printf format
* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
HCR_EL2 is a 64-bit Hypervisor Configuration Register.
gas/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/sysreg-6.d: New test.
* testsuite/gas/aarch64/sysreg-6.s: New test.
Always clear the slot 1 if it was assigned to the input file before the
first .file <NUMBER> directive has been seen. Always use as_where to
generate the correct debug infor for preprocessed assembly codes.
PR gas/25878
PR gas/26740
* dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1
here.
(dwarf2_where): Restore as_where.
(dwarf2_directive_filename): Clear the slot 1 if it was assigned
to the input file.
* testsuite/gas/i386/dwarf5-line-2.d: New file.
* testsuite/gas/i386/dwarf5-line-2.s: Likewise.
* testsuite/gas/i386/dwarf5-line-3.d: Likewise.
* testsuite/gas/i386/dwarf5-line-3.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
dwarf5-line-3.
Some instructions can be emitted (dwarf2_emit_insn is called) before the
first .file <NUMBER> directive has been seen, which allocates the input
file as the first file entry. Reuse the input file entry in the file
table.
PR gas/25878
PR gas/26740
* dwarf2dbg.c (file_entry): Remove auto_assigned.
(assign_file_to_slot): Remove the auto_assign argument.
(allocate_filenum): Updated.
(allocate_filename_to_slot): Reuse the input file entry in the
file table.
(dwarf2_where): Replace as_where with as_where_physical.
* testsuite/gas/i386/dwarf5-line-1.d: New file.
* testsuite/gas/i386/dwarf5-line-1.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
This patch fixes a bogus use of type punning in parse_barrier() which
was causing an assembly failure on big endian LP64 hosts when attempting
to assemble "isb sy" for AArch64.
The type of the entries in aarch64_barrier_opt_hsh is
aarch64_name_value_pair. We were incorrectly casting this to the
locally-defined asm_barrier_opt which has a wider type (on LP64) for the
second member. This happened to work on little-endian hosts but fails on
LP64 big endian.
The fix is to use the correct type in parse_barrier(). This makes the
locally-defined asm_barrier_opt redundant, so remove it.
gas/ChangeLog:
* config/tc-aarch64.c (asm_barrier_opt): Delete.
(parse_barrier): Fix bogus type punning.
* testsuite/gas/aarch64/system.d: Update disassembly.
* testsuite/gas/aarch64/system.s: Add isb sy test.
PR 26692
* config/tc-z80.c (md_begin): Ensure that xpressions are empty
before using them.
(unify_indexed): Likewise.
(z80_start_line_hook): Improve hash sign handling when SDCC
compatibility mode enabled.
(md_parse_exp_not_indexed): Improve indirect addressing
detection.
(md_pseudo_table): Accept hd64 as an alias of z810.
This is feature flags update for Cortex-X1 CPU.
For more information about this processor, see [0].
[0] : https://www.arm.com/products/cortex-x
gas/ChangeLog:
2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* config/tc-aarch64.c: Update Cortex-X1 feature flags.
This is feature flags update for Cortex-X1 CPU.
For more information about this processor, see [0].
[0] : https://www.arm.com/products/cortex-x
gas/ChangeLog:
2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* config/tc-arm.c: Update Cortex-X1 feature flags.
In 64bit, assembler generates a warning for "sysret":
$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'
Always display suffix for %LQ in 64bit to display "sysretl".
gas/
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
The MODRM byte can be checked to display the instruction name only if the
MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that
modrm field checks in putop like, modrm.mod == N with N != 0, can be done
without checking need_modrm.
gas/
PR binutils/26705
* testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
sysretq.
* testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
opcodes/
PR binutils/26705
* i386-dis.c (print_insn): Clear modrm if not needed.
(putop): Check need_modrm for modrm.mod != 3. Don't check
need_modrm for modrm.mod == 3.
PR 26253
gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for
the "o" section flag. Interpret it as a section index. Allow an
index of zero.
* doc/as.texi: Document the new behaviour.
* NEWS: Mention the new feature. Tidy entries.
* testsuite/gas/elf/sh-link-zero.s: New test.
* testsuite/gas/elf/sh-link-zero.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/section21.l: Updated expected assembler
output.
bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an
sh_link value of zero when the SLF_LINK_ORDER flag is set.
(assign_section_numbers): Likewise.
When the address size prefix applies to both the memory and the register
operand, we need to extract the address size prefix from the register
operand if the memory operand has no real registers, like symbol, DISP
or symbol(%rip).
NB: GCC always generates symbol(%rip) for RIP-relative addressing for
both x32 and x86-64.
Move the .code16 tests in movdir.s to movdir-16bit to show the correct
output from objdump.
PR gas/26685
* config/tc-i386.c (process_suffix): Also check the register
operand for the address size prefix if the memory operand has
no real registers.
* testsuite/gas/i386/enqcmd-16bit.d: New file.
* testsuite/gas/i386/enqcmd-16bit.s: Likewise.
* testsuite/gas/i386/movdir-16bit.d: Likewise.
* testsuite/gas/i386/movdir-16bit.s: Likewise.
* testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/movdir.s: Add tests with symbol and DISP.
Remove the .code16 test.
* testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/enqcmd-intel.d: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/movdir-intel.d: Likewise.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* config/obj-elf (elf_pseudo_table): Add attach_to_group.
(obj_elf_attach_to_group): New function.
* doc/as.texi: Document the new directive.
* NEWS: Mention the new feature.
* testsuite/gas/elf/attach-1.s: New test.
* testsuite/gas/elf/attach-1.d: New test driver.
* testsuite/gas/elf/attach-2.s: New test.
* testsuite/gas/elf/attach-2.d: New test driver.
* testsuite/gas/elf/attach-err.s: New test.
* testsuite/gas/elf/attach-err.d: New test driver.
* testsuite/gas/elf/attach-err.err: New test error output.
* testsuite/gas/elf/elf.exp: Run the new tests.
If the address prefix changes the register operand, we need to check the
register operand when the memory operand is RIP-relative.
PR gas/26685
* config/tc-i386.c (process_suffix): Check the register operand
for the address size prefix if the memory operand is symbol(%rip).
* testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative
addressing.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2.
* doc/c-aarch64.texi: Document support for Neoverse N2.
gas * testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
gas * testsuite/gas/aarch64/trbe-invalid.d: New test.
* testsuite/gas/aarch64/trbe-invalid.l: New test.
* testsuite/gas/aarch64/trbe-invalid.s: New test.
* testsuite/gas/aarch64/trbe.d: New test.
* testsuite/gas/aarch64/trbe.s: New test.
opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
This simple follow-on patch adds a feature bit (FP16) that was missing
from the initial Neoverse V1 support.
gas/ChangeLog:
* config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
This simple follow-on patch groups the Neoverse cores together and adds
a missing feature bit (F16) to the entry for Neoverse V1.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores
together, add missing F16 bit to Neoverse V1.
Emit an error instead of crashing in frag_new, handling this same as the
i386 port.
gas/
PR 26400
* config/tc-riscv.c (append_insn): If in absolute section, emit
error before add_relaxed_insn call.
* testsuite/gas/riscv/absolute-sec.d: New.
* testsuite/gas/riscv/absolute-sec.l: New.
* testsuite/gas/riscv/absolute-sec.s: New.
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (arm_cpus): Add Neoverse V1.
* doc/c-arm.texi: Document Neoverse V1 support.
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1.
* doc/c-aarch64.texi: Document Neoverse V1 support.
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The
Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the
AArch32 assembler.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (arm_cpus): Add Neoverse N2.
* doc/c-arm.texi: Document -mcpu=neoverse-n2.
Add option parser for disassembler, and refine the codes of
parse register operand and disassemble register operand.
While strengthen the operands legality check of some instructions.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (parse_type_ctrlreg): Use function
csky_get_control_regno to operand.
(csky_get_reg_val): Likewise.
(is_reg_sp_with_bracket): Use function csky_get_reg_val
to parse operand.
(is_reg_sp): Refine.
(is_oimm_within_range): Fix, report error when operand
is not constant.
(parse_type_cpreg): Refine.
(parse_type_cpcreg): Refine.
(get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
(md_assemble): Fix no error reporting somtimes when
operands number are not fit.
(csky_addc64): Refine.
(csky_subc64): Refine.
(csky_or64): Refine.
(v1_work_fpu_fo): Refine.
(v1_work_fpu_read): Refine.
(v1_work_fpu_writed): Refine.
(v1_work_fpu_readd): Refine.
(v2_work_addc): New function, strengthen the operands legality
check of addc.
* gas/testsuite/gas/csky/all.d : Use register number format when
disassemble register name by default.
* gas/testsuite/gas/csky/cskyv2_all.d : Likewise.
* gas/testsuite/gas/csky/trust.d: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d : Fix.
* gas/testsuite/gas/csky/trust.s : Fix.
opcodes/
* csky-dis.c (using_abi): New.
(parse_csky_dis_options): New function.
(get_gr_name): New function.
(get_cr_name): New function.
(csky_output_operand): Use get_gr_name and get_cr_name to
disassemble and add handle of OPRND_TYPE_IMM5b_LS.
(print_insn_csky): Parse disassembler options.
* opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
(GENARAL_REG_BANK): Define.
(REG_SUPPORT_ALL): Define.
(REG_SUPPORT_ALL): New.
(ASH): Define.
(REG_SUPPORT_A): Define.
(REG_SUPPORT_B): Define.
(REG_SUPPORT_C): Define.
(REG_SUPPORT_D): Define.
(REG_SUPPORT_E): Define.
(csky_abiv1_general_regs): New.
(csky_abiv1_control_regs): New.
(csky_abiv2_general_regs): New.
(csky_abiv2_control_regs): New.
(get_register_name): New function.
(get_register_number): New function.
(csky_get_general_reg_name): New function.
(csky_get_general_regno): New function.
(csky_get_control_reg_name): New function.
(csky_get_control_regno): New function.
(csky_v2_opcodes): Prefer two oprerans format for bclri and
bseti, strengthen the operands legality check of addc, zext
and sext.
This patch corrects "size" and "bitsize" in R_RISCV_RVC_* reloc howtos
so that elfnn-riscv.c:perform_relocation doesn't access past the end
of a section. I've also corrected "size" in the R_RISCV_CALL* reloc
howtos since these relocs apply to two consecutive instructions. That
caused fallout in the assembler with complaints about "fixup not
contained within frag" due to tc-riscv.c:append_insn finishing off a
frag after the auipc insn making up a "call" macro. Which is a little
rude since the CALL reloc also relocates the following jalr. Fixed by
changing the frag handling a little.
I've also changed R_RISCV_ALIGN and R_RISCV_TPREL_ADD marker reloc
howtos to look like R_RISCV_NONE, and corrected dst_mask for numerous
relocs, not that it matters very much.
bfd/
PR 26569
* elfxx-riscv.c (howto_table): Correct size and bitsize of
R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, and R_RISCV_RVC_LUI.
Correct size for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPREL32,
R_RISCV_CALL, and R_RISCV_CALL_PLT. Make R_RISCV_TPREL_ADD and
R_RISCV_ALIGN like R_RISCV_NONE. Correct dst_mask many relocs.
gas/
* config/tc-riscv.c (append_insn): Don't tie off frags at CALL
relocs.
(riscv_call): Tie them off after the jalr.
(md_apply_fix): Zero fx_size of RELAX fixup.
Add gas and opcodes support for two xBPF-exclusive ALU operations:
SDIV (signed division) and SMOD (signed modulo), and add tests for
them in gas.
cpu/
* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
(define-alu-insn-bin, daib): Take ISAs as an argument.
(define-alu-instructions): Update calls to daib pmacro with
ISAs; add sdiv and smod.
gas/
* testsuite/gas/bpf/alu-xbpf.d: New file.
* testsuite/gas/bpf/alu-xbpf.s: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testuiste/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
I removed a few too many parentheses in git commit 7af677524e. This
patch fixes that problem, rewriting the expression so it won't happen
again. The patch also avoids more UB with shifts of signed values.
PR 26610
* config/tc-arm.c (move_or_literal_pool): Correct extraction of
bignum. Use unsigned "v"
(is_double_a_single): Make "v" and "mantissa" unsigned. Formatting.
(double_to_single): Likewise.
* read.c (s_nop): New function. Handles the .nop directive.
(potable): Add entry for "nop".
(s_nops): Code tidy.
* read.h (s_nop): Add prototype.
* config/tc-bpf.h (md_single_noop_insn): Define.
* config/tc-mmix.h (md_single_noop_insn): Define.
* config/tc-or1k.h (md_single_noop_insn): Define.
* config/tc-s12z.c (md_assemble): Preserve the input line pointer,
rather than corrupting it.
* write.c (relax_segment): Update error message regarding
non-absolute values passed to .fill and .nops.
* NEWS: Mention the new directive.
* doc/as.texi: Document the new directive.
* doc/internals.texi: Document the new internal macros used to
implement the new directive.
* testsuite/gas/all/nop.s: New test.
* testsuite/gas/all/nop.d: New test control file.
* testsuite/gas/all/gas.exp: Run the new test.
* testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test.
* testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test
control file.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/space1.l: Adjust expected output.
When -g was used to generate DWARF gas would error out when a .debug_line
already exists. But when a .debug_info section already exists it would
simply skip generating one without warning or error. Do the same for
.debug_line. It is only an error when the user explicitly uses .loc
directives and also generates the .debug_line table itself.
The tests are unfortunately arch specific because the line table is only
generated when actual instructions have been emitted. Use i386 because
that is probably the most used architecture. Before this patch the new
dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't
try to add its own line table).
gas/ChangeLog:
* as.texi (-g): Explicitly mention when .debug_info and .debug_line
are generated for the DWARF format.
(Loc): Add that it is an error to both use a .loc directive and
generate a .debug_line yourself.
* dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable.
(dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE.
(dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting
an error. Only create .debug_line if it is empty (or doesn't exist).
* testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing
an elf target.
* testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
