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aarch64: Add CSR PDEC instruction

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This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.

Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.

CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.

gas/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Update docs.
	* config/tc-aarch64.c (parse_csr_operand): New operand parser.
	(parse_operands): Call to CSR operand parser.
	* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
	* testsuite/gas/aarch64/csre_csr.d: New test.
	* testsuite/gas/aarch64/csre_csr.s: New test.

include/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
	(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.

opcodes/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
	* aarch64-tbl.h (CSRE): New CSRE feature handler.
	(_CSRE_INSN): New CSRE instruction type.
	(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
This commit is contained in:
Przemyslaw Wirkus 2020-10-28 14:16:39 +00:00
parent 82503ca7ed
commit dd4a72c859
13 changed files with 1489 additions and 1417 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
gas/NEWS
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@ -24,6 +24,9 @@
* Add support for DSB memory nXS barrier and WFET instruction for Armv8.7
AArch64.
* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
feature.
* Add support for Intel TDX instructions.
* Add support for Intel Key Locker instructions.

31
gas/config/tc-aarch64.c
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@ -4036,6 +4036,29 @@ parse_barrier_psb (char **str,
return 0;
}
/* Parse an operand for CSR (CSRE instruction). */
static int
parse_csr_operand (char **str)
{
char *p, *q;
p = q = *str;
while (ISALPHA (*q))
q++;
/* Instruction has only one operand PDEC which encodes Rt field of the
operation to 0b11111. */
if (strcasecmp(p, "pdec"))
{
set_syntax_error (_("CSR instruction accepts only PDEC"));
return PARSE_FAIL;
}
*str = q;
return 0;
}
/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
return 0 if successful. Otherwise return PARSE_FAIL. */
@ -6749,6 +6772,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
break;
case AARCH64_OPND_CSRE_CSR:
val = parse_csr_operand (&str);
if (val == PARSE_FAIL)
goto failure;
break;
default:
as_fatal (_("unhandled operand code %d"), operands[i]);
}
@ -9171,6 +9200,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
{"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
{"csre", AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0),
AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};

3
gas/testsuite/gas/aarch64/csre_csr-invalid.d Normal file
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@ -0,0 +1,3 @@
#name: CSR PDEC instruction
#source: csre_csr-invalid.s
#error_output: csre_csr-invalid.l

2
gas/testsuite/gas/aarch64/csre_csr-invalid.l Normal file
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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Error: selected processor does not support `csr pdec'

4
gas/testsuite/gas/aarch64/csre_csr-invalid.s Normal file
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@ -0,0 +1,4 @@
/* CSR PDEC requires +csre for -march= command line option. */
.arch armv8-a
csr pdec

10
gas/testsuite/gas/aarch64/csre_csr.d Normal file
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@ -0,0 +1,10 @@
#name: CSRE extension CSR PDEC instruction
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d50b721f csr pdec
.*: d50b721f csr pdec

4
gas/testsuite/gas/aarch64/csre_csr.s Normal file
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@ -0,0 +1,4 @@
.arch armv8-a+csre
csr pdec
CSR PDEC

2
include/opcode/aarch64.h
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@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
@ -432,6 +433,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
};
/* Qualifier constrains an operand. It either specifies a variant of an

244
opcodes/aarch64-asm-2.c
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@ -426,174 +426,174 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1184: /* movz */
value = 1184; /* --> movz. */
break;
case 1241: /* autibsp */
case 1240: /* autibz */
case 1239: /* autiasp */
case 1238: /* autiaz */
case 1237: /* pacibsp */
case 1236: /* pacibz */
case 1235: /* paciasp */
case 1234: /* paciaz */
case 1211: /* tsb */
case 1210: /* psb */
case 1209: /* esb */
case 1208: /* autib1716 */
case 1207: /* autia1716 */
case 1206: /* pacib1716 */
case 1205: /* pacia1716 */
case 1204: /* xpaclri */
case 1202: /* sevl */
case 1201: /* sev */
case 1200: /* wfi */
case 1199: /* wfe */
case 1198: /* yield */
case 1197: /* bti */
case 1196: /* csdb */
case 1195: /* nop */
case 1194: /* hint */
value = 1194; /* --> hint. */
break;
case 1217: /* pssbb */
case 1216: /* ssbb */
case 1215: /* dfb */
case 1213: /* dsb */
value = 1213; /* --> dsb. */
case 1242: /* autibsp */
case 1241: /* autibz */
case 1240: /* autiasp */
case 1239: /* autiaz */
case 1238: /* pacibsp */
case 1237: /* pacibz */
case 1236: /* paciasp */
case 1235: /* paciaz */
case 1212: /* tsb */
case 1211: /* psb */
case 1210: /* esb */
case 1209: /* autib1716 */
case 1208: /* autia1716 */
case 1207: /* pacib1716 */
case 1206: /* pacia1716 */
case 1205: /* xpaclri */
case 1203: /* sevl */
case 1202: /* sev */
case 1201: /* wfi */
case 1200: /* wfe */
case 1199: /* yield */
case 1198: /* bti */
case 1197: /* csdb */
case 1196: /* nop */
case 1195: /* hint */
value = 1195; /* --> hint. */
break;
case 1218: /* pssbb */
case 1217: /* ssbb */
case 1216: /* dfb */
case 1214: /* dsb */
value = 1214; /* --> dsb. */
break;
case 1229: /* cpp */
case 1228: /* dvp */
case 1227: /* cfp */
case 1225: /* tlbi */
case 1224: /* ic */
case 1223: /* dc */
case 1222: /* at */
case 1221: /* sys */
value = 1221; /* --> sys. */
case 1215: /* dsb */
value = 1215; /* --> dsb. */
break;
case 1226: /* wfet */
value = 1226; /* --> wfet. */
case 1230: /* cpp */
case 1229: /* dvp */
case 1228: /* cfp */
case 1226: /* tlbi */
case 1225: /* ic */
case 1224: /* dc */
case 1223: /* at */
case 1222: /* sys */
value = 1222; /* --> sys. */
break;
case 2039: /* bic */
case 1289: /* and */
value = 1289; /* --> and. */
case 1227: /* wfet */
value = 1227; /* --> wfet. */
break;
case 1272: /* mov */
case 1291: /* and */
value = 1291; /* --> and. */
case 2040: /* bic */
case 1290: /* and */
value = 1290; /* --> and. */
break;
case 1276: /* movs */
case 1292: /* ands */
value = 1292; /* --> ands. */
case 1273: /* mov */
case 1292: /* and */
value = 1292; /* --> and. */
break;
case 2040: /* cmple */
case 1327: /* cmpge */
value = 1327; /* --> cmpge. */
case 1277: /* movs */
case 1293: /* ands */
value = 1293; /* --> ands. */
break;
case 2043: /* cmplt */
case 1330: /* cmpgt */
value = 1330; /* --> cmpgt. */
case 2041: /* cmple */
case 1328: /* cmpge */
value = 1328; /* --> cmpge. */
break;
case 2041: /* cmplo */
case 1332: /* cmphi */
value = 1332; /* --> cmphi. */
case 2044: /* cmplt */
case 1331: /* cmpgt */
value = 1331; /* --> cmpgt. */
break;
case 2042: /* cmpls */
case 1335: /* cmphs */
value = 1335; /* --> cmphs. */
case 2042: /* cmplo */
case 1333: /* cmphi */
value = 1333; /* --> cmphi. */
break;
case 1269: /* mov */
case 1357: /* cpy */
value = 1357; /* --> cpy. */
case 2043: /* cmpls */
case 1336: /* cmphs */
value = 1336; /* --> cmphs. */
break;
case 1271: /* mov */
case 1270: /* mov */
case 1358: /* cpy */
value = 1358; /* --> cpy. */
break;
case 2050: /* fmov */
case 1274: /* mov */
case 1272: /* mov */
case 1359: /* cpy */
value = 1359; /* --> cpy. */
break;
case 1264: /* mov */
case 1371: /* dup */
value = 1371; /* --> dup. */
case 2051: /* fmov */
case 1275: /* mov */
case 1360: /* cpy */
value = 1360; /* --> cpy. */
break;
case 1266: /* mov */
case 1263: /* mov */
case 1265: /* mov */
case 1372: /* dup */
value = 1372; /* --> dup. */
break;
case 2049: /* fmov */
case 1268: /* mov */
case 1267: /* mov */
case 1264: /* mov */
case 1373: /* dup */
value = 1373; /* --> dup. */
break;
case 1267: /* mov */
case 1374: /* dupm */
value = 1374; /* --> dupm. */
case 2050: /* fmov */
case 1269: /* mov */
case 1374: /* dup */
value = 1374; /* --> dup. */
break;
case 2044: /* eon */
case 1376: /* eor */
value = 1376; /* --> eor. */
case 1268: /* mov */
case 1375: /* dupm */
value = 1375; /* --> dupm. */
break;
case 1277: /* not */
case 1378: /* eor */
value = 1378; /* --> eor. */
case 2045: /* eon */
case 1377: /* eor */
value = 1377; /* --> eor. */
break;
case 1278: /* nots */
case 1379: /* eors */
value = 1379; /* --> eors. */
case 1278: /* not */
case 1379: /* eor */
value = 1379; /* --> eor. */
break;
case 2045: /* facle */
case 1384: /* facge */
value = 1384; /* --> facge. */
case 1279: /* nots */
case 1380: /* eors */
value = 1380; /* --> eors. */
break;
case 2046: /* faclt */
case 1385: /* facgt */
value = 1385; /* --> facgt. */
case 2046: /* facle */
case 1385: /* facge */
value = 1385; /* --> facge. */
break;
case 2047: /* fcmle */
case 1398: /* fcmge */
value = 1398; /* --> fcmge. */
case 2047: /* faclt */
case 1386: /* facgt */
value = 1386; /* --> facgt. */
break;
case 2048: /* fcmlt */
case 1400: /* fcmgt */
value = 1400; /* --> fcmgt. */
case 2048: /* fcmle */
case 1399: /* fcmge */
value = 1399; /* --> fcmge. */
break;
case 2049: /* fcmlt */
case 1401: /* fcmgt */
value = 1401; /* --> fcmgt. */
break;
case 1262: /* fmov */
case 1407: /* fcpy */
value = 1407; /* --> fcpy. */
break;
case 1261: /* fmov */
case 1406: /* fcpy */
value = 1406; /* --> fcpy. */
case 1430: /* fdup */
value = 1430; /* --> fdup. */
break;
case 1260: /* fmov */
case 1429: /* fdup */
value = 1429; /* --> fdup. */
break;
case 1262: /* mov */
case 1760: /* orr */
value = 1760; /* --> orr. */
break;
case 2051: /* orn */
case 1263: /* mov */
case 1761: /* orr */
value = 1761; /* --> orr. */
break;
case 1265: /* mov */
case 1763: /* orr */
value = 1763; /* --> orr. */
case 2052: /* orn */
case 1762: /* orr */
value = 1762; /* --> orr. */
break;
case 1275: /* movs */
case 1764: /* orrs */
value = 1764; /* --> orrs. */
case 1266: /* mov */
case 1764: /* orr */
value = 1764; /* --> orr. */
break;
case 1270: /* mov */
case 1826: /* sel */
value = 1826; /* --> sel. */
case 1276: /* movs */
case 1765: /* orrs */
value = 1765; /* --> orrs. */
break;
case 1273: /* mov */
case 1271: /* mov */
case 1827: /* sel */
value = 1827; /* --> sel. */
break;
case 1274: /* mov */
case 1828: /* sel */
value = 1828; /* --> sel. */
break;
default: return NULL;
}

2575
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

16
opcodes/aarch64-opc-2.c
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@ -311,17 +311,17 @@ static const unsigned op_enum_table [] =
391,
413,
415,
1265,
1270,
1263,
1262,
1266,
1273,
1275,
1271,
1264,
1263,
1267,
1274,
1276,
1272,
1278,
1277,
1273,
1279,
1278,
131,
};

4
opcodes/aarch64-opc.c
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@ -3787,6 +3787,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s", opnd->hint_option->name);
break;
case AARCH64_OPND_CSRE_CSR:
snprintf (buf, size, "pdec");
break;
default:
assert (0);
}

8
opcodes/aarch64-tbl.h
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@ -2410,6 +2410,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
| AARCH64_FEATURE_SVE, 0);
static const aarch64_feature_set aarch64_feature_v8_r =
AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
static const aarch64_feature_set aarch64_feature_csre =
AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0);
#define CORE &aarch64_feature_v8
@ -2456,6 +2458,7 @@ static const aarch64_feature_set aarch64_feature_v8_r =
#define I8MM &aarch64_feature_i8mm
#define ARMV8_R &aarch64_feature_v8_r
#define ARMV8_7 &aarch64_feature_v8_7
#define CSRE &aarch64_feature_csre
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -2563,6 +2566,9 @@ static const aarch64_feature_set aarch64_feature_v8_r =
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
#define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _CSRE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, CSRE, OPS, QUALS, FLAGS, 0, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
@ -3833,6 +3839,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
_TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
_TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
/* CSRE Instructions. */
_CSRE_INSN ("csr", 0xd50b721f, 0xffffffff, 0, OP1 (CSRE_CSR), {}, 0),
/* System. */
CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),