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This patch introduces ETE (Embedded Trace Extension) system registers for the AArch64 architecture.

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gas           * testsuite/gas/aarch64/ete.d: New test.
              * testsuite/gas/aarch64/ete.s: New test.

opcodes       * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
This commit is contained in:
Przemyslaw Wirkus 2020-09-28 15:41:23 +01:00 committed by Nick Clifton
parent 1ff8e40105
commit 3454861d89
5 changed files with 48 additions and 0 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/trbe-invalid.d: New test.

18
gas/testsuite/gas/aarch64/ete.d Normal file
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@ -0,0 +1,18 @@
#name: ETE System registers
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
[^:]+: d5310880 mrs x0, trcextinselr0
[^:]+: d5310980 mrs x0, trcextinselr1
[^:]+: d5310a80 mrs x0, trcextinselr2
[^:]+: d5310b80 mrs x0, trcextinselr3
[^:]+: d5310a00 mrs x0, trcrsr
[^:]+: d5110880 msr trcextinselr0, x0
[^:]+: d5110980 msr trcextinselr1, x0
[^:]+: d5110a80 msr trcextinselr2, x0
[^:]+: d5110b80 msr trcextinselr3, x0
[^:]+: d5110a00 msr trcrsr, x0

15
gas/testsuite/gas/aarch64/ete.s Normal file
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@ -0,0 +1,15 @@
/* ETE System registers. */
/* Read from system register. */
mrs x0, trcextinselr0
mrs x0, trcextinselr1
mrs x0, trcextinselr2
mrs x0, trcextinselr3
mrs x0, trcrsr
/* Write to system register. */
msr trcextinselr0, x0
msr trcextinselr1, x0
msr trcextinselr2, x0
msr trcextinselr3, x0
msr trcrsr, x0

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,

6
opcodes/aarch64-opc.c
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@ -4319,6 +4319,12 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0),
SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0),
SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0),
SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0),
SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0),
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};