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PE/x86-64: Display PE relocation names

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For PE/x86-64, display PE relocation names:

R_X86_64_64   -> IMAGE_REL_AMD64_ADDR64
R_X86_64_32   -> IMAGE_REL_AMD64_ADDR32.
rva32         -> IMAGE_REL_AMD64_ADDR32NB
R_X86_64_PC32 -> IMAGE_REL_AMD64_REL32
DISP32+1      -> IMAGE_REL_AMD64_REL32_1
DISP32+2      -> IMAGE_REL_AMD64_REL32_2
DISP32+3      -> IMAGE_REL_AMD64_REL32_3
DISP32+4      -> IMAGE_REL_AMD64_REL32_4
DISP32+5      -> IMAGE_REL_AMD64_REL32_5
secrel32      -> IMAGE_REL_AMD64_SECREL

bfd/

	* coff-x86_64.c (howto_table): Display PE relocation names.

gas/

	* testsuite/gas/cfi/reloc-pe-i386.d: Updated.
	* testsuite/gas/i386/x86-64-w64-pcrel.d: Likewise.
This commit is contained in:
H.J. Lu 2020-09-15 13:56:18 -07:00
parent 0403e9ccae
commit ec6653d824
5 changed files with 25 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bfd/ChangeLog
View File

@ -1,3 +1,7 @@
2020-09-15 H.J. Lu <hongjiu.lu@intel.com>
* coff-x86_64.c (howto_table): Display PE relocation names.
2020-09-15 Hans-Peter Nilsson <hp@axis.com>
PR ld/26589

22
bfd/coff-x86_64.c
View File

@ -222,7 +222,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"R_X86_64_64", /* name */
"IMAGE_REL_AMD64_ADDR64", /* name */
TRUE, /* partial_inplace */
0xffffffffffffffffll, /* src_mask */
0xffffffffffffffffll, /* dst_mask */
@ -235,7 +235,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"R_X86_64_32", /* name */
"IMAGE_REL_AMD64_ADDR32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -249,7 +249,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"rva32", /* name */
"IMAGE_REL_AMD64_ADDR32NB", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -263,7 +263,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"R_X86_64_PC32", /* name */
"IMAGE_REL_AMD64_REL32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -277,7 +277,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"DISP32+1", /* name */
"IMAGE_REL_AMD64_REL32_1", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -290,7 +290,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"DISP32+2", /* name */
"IMAGE_REL_AMD64_REL32_2", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -303,7 +303,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"DISP32+3", /* name */
"IMAGE_REL_AMD64_REL32_3", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -316,7 +316,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"DISP32+4", /* name */
"IMAGE_REL_AMD64_REL32_4", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -329,7 +329,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"DISP32+5", /* name */
"IMAGE_REL_AMD64_REL32_5", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -345,7 +345,7 @@ static reloc_howto_type howto_table[] =
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_amd64_reloc, /* special_function */
"secrel32", /* name */
"IMAGE_REL_AMD64_SECREL", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
@ -896,4 +896,4 @@ const bfd_target
&bigobj_swap_table
};
#endif
#endif

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-09-15 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/cfi/reloc-pe-i386.d: Updated.
* testsuite/gas/i386/x86-64-w64-pcrel.d: Likewise.
2020-09-15 Alan Modra <amodra@gmail.com>
PR 26610

2
gas/testsuite/gas/cfi/reloc-pe-i386.d
View File

@ -3,7 +3,7 @@
#...
RELOCATION RECORDS FOR \[.debug_frame\]:
OFFSET .* TYPE .* VALUE
0.* secrel32 .* .debug_frame
0.* (secrel32|IMAGE_REL_AMD64_SECREL) .* .debug_frame
0.* .* .text

8
gas/testsuite/gas/i386/x86-64-w64-pcrel.d
View File

@ -9,12 +9,12 @@ Disassembly of section .text:
0+000 <_start>:
[ ]*[0-9a-f]+:[ ]+b0 02[ ]+movb?[ ]+\$(0x)?2,%al[ ]*[0-9a-f]+:[ ]+R_X86_64_PC8[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+66 b8 04 00[ ]+movw?[ ]+\$(0x)?4,%ax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC16[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+b8 05( 00){3}[ ]+movl?[ ]+\$(0x)?5,%eax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 c7 c0 07( 00){3}[ ]+movq?[ ]+\$(0x)?7,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+b8 05( 00){3}[ ]+movl?[ ]+\$(0x)?5,%eax[ ]*[0-9a-f]+:[ ]+IMAGE_REL_AMD64_REL32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 c7 c0 07( 00){3}[ ]+movq?[ ]+\$(0x)?7,%rax[ ]*[0-9a-f]+:[ ]+IMAGE_REL_AMD64_REL32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 b8 0a( 00){7}[ ]+mov(abs)?q?[ ]+\$(0x)?a,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC64[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+b0 00[ ]+movb?[ ]+\$(0x)?0,%al[ ]*[0-9a-f]+:[ ]+R_X86_64_8[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+movw?[ ]+\$(0x)?0,%ax[ ]*[0-9a-f]+:[ ]+R_X86_64_16[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+b8( 00){4}[ ]+movl?[ ]+\$(0x)?0,%eax[ ]*[0-9a-f]+:[ ]+R_X86_64_32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+b8( 00){4}[ ]+movl?[ ]+\$(0x)?0,%eax[ ]*[0-9a-f]+:[ ]+IMAGE_REL_AMD64_ADDR32[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 c7 c0( 00){4}[ ]+movq?[ ]+\$(0x)?0,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_32S[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 b8( 00){8}[ ]+mov(abs)?q?[ ]+\$(0x)?0,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_64[ ]+xtrn
[ ]*[0-9a-f]+:[ ]+48 b8( 00){8}[ ]+mov(abs)?q?[ ]+\$(0x)?0,%rax[ ]*[0-9a-f]+:[ ]+IMAGE_REL_AMD64_ADDR64[ ]+xtrn
#pass