1260 lines
34 KiB
Markdown
1260 lines
34 KiB
Markdown
;;- Machine description for GNU compiler
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;;- MIL-STD-1750A version.
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;; Copyright (C) 1994 Free Software Foundation, Inc.
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;; Contributed by O.M.Kellogg, DASA (okellogg@salyko.cube.net).
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;; This file is part of GNU CC.
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 1, or (at your option)
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;; any later version.
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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;;- instruction definitions
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;- When naming insn's (operand 0 of define_insn) be careful about using
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;;- names from other targets machine descriptions.
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;; MIL-STD-1750 specific remarks:
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;;
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;; 1) BITS_PER_UNIT = 16
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;;
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;; 2) GCC to MIL-STD-1750 data type mappings:
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;; QImode => single integer (16 bits or 1 reg).
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;; HImode => double integer (32 bits or 2 regs).
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;; HFmode => single precision float (32 bits or 2 regs).
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;; TQFmode => extended precision float (48 bits or 3 regs).
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;;
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;; 3) Immediate integer operands Constraints:
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;; 'I' 1 .. 16
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;; 'J' -1 ..-16
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;; 'K' 0 .. 15
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;; 'L' 0 .. 255
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;; 'M' -32768 .. 32767
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;; 'O' => 0 (for optimizations and GCC quirks)
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;;
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;; Further notes:
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;;- Assembly output ending in ".M" are macros in file M1750.INC
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;; stackpush
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(define_insn ""
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[(set (match_operand:QI 0 "push_operand" "=<")
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(match_operand:QI 1 "general_operand" "r"))]
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""
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"pshm r%1,r%1")
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(define_insn ""
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[(set (match_operand:HI 0 "push_operand" "=<")
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(match_operand:HI 1 "general_operand" "r"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[1];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
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} ")
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(define_insn ""
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[(set (match_operand:HF 0 "push_operand" "=<")
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(match_operand:HF 1 "general_operand" "r"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[1];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
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output_asm_insn(\"pshm r%0,r%1\",new_operands);
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return \"\;\";
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} ")
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(define_insn ""
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[(set (match_operand:TQF 0 "push_operand" "=<")
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(match_operand:TQF 1 "general_operand" "r"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[1];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
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output_asm_insn(\"pshm r%0,r%1\",new_operands);
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return \"\;\";
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} ")
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;; stackpop
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(define_insn ""
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[(set (match_operand:QI 0 "general_operand" "=r")
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(match_operand:QI 1 "push_operand" ">"))]
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""
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"popm r%1,r%1")
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(define_insn ""
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[(set (match_operand:HI 0 "general_operand" "=r")
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(match_operand:HI 1 "push_operand" ">"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[0];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
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output_asm_insn(\"popm r%0,r%1\",new_operands);
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return \"\;\";
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} ")
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(define_insn ""
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[(set (match_operand:HF 0 "general_operand" "=r")
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(match_operand:HF 1 "push_operand" ">"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[0];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
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output_asm_insn(\"popm r%0,r%1\",new_operands);
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return \"\;\";
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} ")
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(define_insn ""
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[(set (match_operand:TQF 0 "general_operand" "=r")
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(match_operand:TQF 1 "push_operand" ">"))]
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""
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"*
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{
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rtx new_operands[2];
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new_operands[0] = operands[0];
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new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
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output_asm_insn(\"popm r%0,r%1\",new_operands);
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return \"\;\";
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} ")
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;; Test operations. These shouldn't really occur for 1750:
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;; all important instructions set the cc's (see NOTICE_UPDATE_CC)
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(define_insn "tstqi"
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[(set (cc0)
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(match_operand:QI 0 "register_operand" "r"))]
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""
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"lr r%0,r%0 ; from tstqi")
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(define_insn "tsthi"
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[(set (cc0)
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(match_operand:HI 0 "register_operand" "r"))]
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""
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"dlr r%0,r%0 ; from tsthi")
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(define_insn "tsthf"
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[(set (cc0)
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(match_operand:HF 0 "register_operand" "r"))]
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""
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"dlr r%0,r%0 ; from tsthf")
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;; This one is happy with "roughly zero" :-) (should be improved)
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(define_insn "tsttqf"
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[(set (cc0)
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(match_operand:TQF 0 "register_operand" "r"))]
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""
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"dlr r%0,r%0 ; from tsttqf")
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;; block move.
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; there is a problem with this insn in gcc-2.2.3
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; (clobber (match_dup 2)) does not prevent use of this operand later
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;
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(define_insn "movstrqi"
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[(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
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(mem:BLK (match_operand:QI 1 "register_operand" "r")))
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(use (match_operand:QI 2 "register_operand" "r"))
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(use (match_operand:QI 3 "immediate_operand" ""))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))]
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""
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"* return (char *)movcnt_regno_adjust(operands); ")
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;; compare instructions.
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(define_insn "cmpqi"
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[(set (cc0)
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(compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
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(match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
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""
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"@
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cisp r%0,%1
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cisn r%0,%J1
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cim r%0,%1
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cr r%0,r%1
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c r%0,%1 ")
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(define_insn "cmphi"
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[(set (cc0)
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(compare (match_operand:HI 0 "general_operand" "r,r")
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(match_operand:HI 1 "general_operand" "r,m")))]
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""
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"@
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dcr r%0,r%1
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dc r%0,%1 ")
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(define_insn "cmphf"
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[(set (cc0)
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(compare (match_operand:HF 0 "general_operand" "r,r")
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(match_operand:HF 1 "general_operand" "r,m")))]
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""
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"@
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fcr r%0,r%1
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fc r%0,%1 ")
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(define_insn "cmptqf"
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[(set (cc0)
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(compare (match_operand:TQF 0 "general_operand" "r,r")
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(match_operand:TQF 1 "general_operand" "r,m")))]
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""
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"@
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efcr r%0,r%1
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efc r%0,%1 ")
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;; truncation instructions
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;;- 1750: any needed?
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(define_insn "trunchiqi2"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(truncate:QI
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(match_operand:HI 1 "register_operand" "r")))]
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""
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"*
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{
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REGNO(operands[1]) += 1;
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return \"lr r%0,r%1 ;trunchiqi2\";
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} ")
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;; zero extension instructions
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r")
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(zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
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""
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"*
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{
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output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands);
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REGNO(operands[0]) += 1;
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switch (which_alternative)
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{
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case 0:
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return \"lr r%0,r%1\";
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case 1:
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return \"l r%0,%1\";
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case 2:
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return \"lim r%0,%1\";
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}
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} ")
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;; sign extension instructions
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r")
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(sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
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""
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"@
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lr r%0,r%1 ;extendqihi2\;dsra r%0,16
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l r%0,%1 ;extendqihi2\;dsra r%0,16
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lim r%0,%1 ;extendqihi2\;dsra r%0,16 ")
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;; Conversions between float and double.
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; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
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(define_insn "extendhftqf2"
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[(set (match_operand:TQF 0 "register_operand" "=r,r")
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(float_extend:TQF
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(match_operand:HF 1 "general_operand" "r,m")))]
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""
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"*
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{
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REGNO(operands[0]) += 2;
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output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",operands);
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REGNO(operands[0]) -= 2;
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if (which_alternative == 0)
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return \"dlr r%0,r%1\";
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else
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return \"dl r%0,%1\";
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} ")
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; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
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(define_insn "trunctqfhf2"
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[(set (match_operand:HF 0 "register_operand" "=r,r")
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(float_truncate:HF
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(match_operand:TQF 1 "general_operand" "r,m")))]
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""
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"@
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dlr r%0,r%1 ;trunctqfhf2
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dl r%0,%1 ;trunctqfhf2 ")
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;; Conversion between fixed point and floating point.
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(define_insn "floatqihf2"
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[(set (match_operand:HF 0 "register_operand" "=r")
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(float:HF (match_operand:QI 1 "register_operand" "r")))]
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""
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"flt r%0,r%1")
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(define_insn "floathitqf2"
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[(set (match_operand:TQF 0 "register_operand" "=r")
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(float:TQF (match_operand:HI 1 "register_operand" "r")))]
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""
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"eflt r%0,r%1")
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;; Convert floats to ints
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(define_insn "fix_trunchfqi2"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
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""
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"fix r%0,r%1")
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(define_insn "fix_trunctqfhi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
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""
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"efix r%0,r%1")
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;; Move instructions
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;; We can't deal with normal byte-size characters, only with WIDE characters!
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;; This may appear as a serious restriction, but it also opens the doors
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;; for ISO 10646 :-)
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;; 16-bit moves
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(define_insn "movqi"
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[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m")
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(match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))]
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""
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"@
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xorr r%0,r%0
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lisp r%0,%1
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lisn r%0,%J1
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lim r%0,%1 ; 'M' constraint
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lim r%0,%1 ; 'i' constraint
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lr r%0,r%1
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l r%0,%1
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st r%1,%0
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stc %1,%0 ")
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;; 32-bit moves
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;; Set HIreg to constant
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(match_operand 1 "immediate_operand" "i"))]
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""
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"*
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if (GET_CODE(operands[1]) == CONST_INT)
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{
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int val = INTVAL(operands[1]);
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if (val >= 0)
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{
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if (val <= 65535)
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{
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output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",operands);
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operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1);
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if (val == 0)
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return \"xorr r%0,r%0\";
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else if (val <= 16)
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return \"lisp r%0,%1\";
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else
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return \"lim r%0,%1\";
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}
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}
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else if (val >= -16)
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return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\";
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INTVAL(operands[1]) >>= 16;
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output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",operands);
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REGNO(operands[0]) += 1;
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INTVAL(operands[1]) = val & 0xFFFF;
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return \"lim r%0,%1\";
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}
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return \"lim r%0,%1\;dsra r%0,16 ;movhi cst\";
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")
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(define_insn "movhi"
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[(set (match_operand:HI 0 "general_operand" "=r,r,m")
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(match_operand:HI 1 "general_operand" "r,m,r"))]
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""
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"@
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dlr r%0,r%1
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dl r%0,%1
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dst r%1,%0 ")
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;; Single-Float moves are *same* as HImode moves:
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;(define_insn "movhf"
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; [(set (match_operand:HF 0 "general_operand" "=r,r,r,m")
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; (match_operand:HF 1 "general_operand" "F,r,m,r"))]
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; ""
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; "@
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; %D1\;dl r%0,%F1
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; dlr r%0,r%1
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; dl r%0,%1
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; dst r%1,%0 ")
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(define_insn "movhf"
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[(set (match_operand:HF 0 "general_operand" "=r,r,m")
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(match_operand:HF 1 "general_operand" "r,m,r"))]
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""
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"@
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dlr r%0,r%1
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dl r%0,%1
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dst r%1,%0 ")
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;; Longfloat moves
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;(define_insn "movtqf"
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; [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
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; (match_operand:TQF 1 "general_operand" "F,r,m,r"))]
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; ""
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; "@
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; %E1\;efl r%0,%G1
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; eflr.m %0,%1
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; efl r%0,%1
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; efst r%1,%0 ")
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(define_insn "movtqf"
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[(set (match_operand:TQF 0 "general_operand" "=r,r,m")
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(match_operand:TQF 1 "general_operand" "r,m,r"))]
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""
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"@
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eflr.m %0,%1
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efl r%0,%1
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efst r%1,%0 ")
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;; add instructions
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;; single integer
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;; Use "LIM Ra,sym,Rb" for adding a symbol value to a register and
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;; transferring the result to a different register.
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;(define_insn ""
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; [(set (match_operand:QI 0 "register_operand" "=r")
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; (plus:QI (match_operand:QI 1 "register_operand" "b")
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; (match_operand:QI 2 "immediate_operand" "i")))]
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; "REGNO(operands[0]) != REGNO(operands[1])"
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; "lim r%0,%2,r%1 ;md special addqi")
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(define_insn "addqi3"
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[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
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(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
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""
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"*
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switch (which_alternative)
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{
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case 0:
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return \"aisp r%0,%2\";
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case 1:
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return \"sisp r%0,%J2\";
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case 2:
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if (INTVAL(operands[2]) < 0)
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return \"sim r%0,%J2\";
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else
|
|
return \"aim r%0,%2\";
|
|
case 3:
|
|
return \"ar r%0,r%2\";
|
|
case 4:
|
|
return \"a r%0,%2\";
|
|
case 5:
|
|
return \"incm %2,%0\";
|
|
case 6:
|
|
return \"decm %J2,%0\";
|
|
} ")
|
|
|
|
;; double integer
|
|
(define_insn "addhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(plus:HI (match_operand:HI 1 "register_operand" "%0,0")
|
|
(match_operand:HI 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
dar r%0,r%2
|
|
da r%0,%2 ")
|
|
|
|
(define_insn "addhf3"
|
|
[(set (match_operand:HF 0 "register_operand" "=r,r")
|
|
(plus:HF (match_operand:HF 1 "register_operand" "%0,0")
|
|
(match_operand:HF 2 "general_operand" "m,r")))]
|
|
""
|
|
"@
|
|
fa r%0,%2
|
|
far r%0,r%2 ")
|
|
|
|
(define_insn "addtqf3"
|
|
[(set (match_operand:TQF 0 "register_operand" "=r,r")
|
|
(plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
|
|
(match_operand:TQF 2 "general_operand" "m,r")))]
|
|
""
|
|
"@
|
|
efa r%0,%2
|
|
efar r%0,r%2 ")
|
|
|
|
|
|
;; subtract instructions
|
|
|
|
;; single integer
|
|
(define_insn "subqi3"
|
|
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
|
|
(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
|
|
(match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
|
|
""
|
|
"@
|
|
sisp r%0,%2
|
|
sim r%0,%2
|
|
sr r%0,r%2
|
|
s r%0,%2
|
|
decm %2,%0 ")
|
|
|
|
;; double integer
|
|
(define_insn "subhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(minus:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:HI 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
dsr r%0,r%2
|
|
ds r%0,%2 ")
|
|
|
|
(define_insn "subhf3"
|
|
[(set (match_operand:HF 0 "register_operand" "=r,r")
|
|
(minus:HF (match_operand:HF 1 "register_operand" "0,0")
|
|
(match_operand:HF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
fsr r%0,r%2
|
|
fs r%0,%2 ")
|
|
|
|
(define_insn "subtqf3"
|
|
[(set (match_operand:TQF 0 "register_operand" "=r,r")
|
|
(minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
|
|
(match_operand:TQF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
efsr r%0,r%2
|
|
efs r%0,%2 ")
|
|
|
|
|
|
;; multiply instructions
|
|
|
|
(define_insn "mulqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
|
|
(mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
|
|
(match_operand:QI 2 "general_operand" "I,J,M,r,m")))]
|
|
""
|
|
"@
|
|
misp r%0,%2
|
|
misn r%0,%J2
|
|
msim r%0,%2
|
|
msr r%0,r%2
|
|
ms r%0,%2 ")
|
|
|
|
|
|
; 32-bit product
|
|
(define_insn "mulqihi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
|
|
(mult:HI (match_operand:QI 1 "register_operand" "%0,0,0")
|
|
(match_operand:QI 2 "general_operand" "M,r,m")))]
|
|
""
|
|
"@
|
|
mim r%0,%1
|
|
mr r%0,r%2
|
|
m r%0,%2 ")
|
|
|
|
(define_insn "mulhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(mult:HI (match_operand:HI 1 "register_operand" "%0,0")
|
|
(match_operand:HI 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
dmr r%0,r%2
|
|
dm r%0,%2 ")
|
|
|
|
; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
|
|
|
|
(define_insn "mulhf3"
|
|
[(set (match_operand:HF 0 "register_operand" "=r,r")
|
|
(mult:HF (match_operand:HF 1 "register_operand" "%0,0")
|
|
(match_operand:HF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
fmr r%0,r%2
|
|
fm r%0,%2 ")
|
|
|
|
(define_insn "multqf3"
|
|
[(set (match_operand:TQF 0 "register_operand" "=r,r")
|
|
(mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
|
|
(match_operand:TQF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
efmr r%0,r%2
|
|
efm r%0,%2 ")
|
|
|
|
|
|
;; divide instructions
|
|
;; The 1750 16bit integer division instructions deliver a 16-bit
|
|
;; quotient and a 16-bit remainder, where the remainder is in the next higher
|
|
;; register number above the quotient. For now, we haven't found a way
|
|
;; to give the reload pass knowledge of this property. So we make do with
|
|
;; whatever registers the allocator wants, and willy-nilly output a pair of
|
|
;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
|
|
;; A comment in the description of `divmodM4' suggests that one leave the divM3
|
|
;; undefined when there is a divmodM4 available.
|
|
|
|
(define_insn "divmodqi4"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
|
|
(div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
|
|
(match_operand:QI 2 "general_operand" "I,J,M,r,m")))
|
|
(set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
|
|
(mod:QI (match_dup 1) (match_dup 2)))]
|
|
""
|
|
"*
|
|
{
|
|
char *istr;
|
|
switch(which_alternative)
|
|
{
|
|
case 0:
|
|
istr = \"disp\";
|
|
break;
|
|
case 1:
|
|
INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */
|
|
istr = \"disn\";
|
|
break;
|
|
case 2:
|
|
istr = \"dvim\";
|
|
break;
|
|
case 3:
|
|
istr = \"dvr \";
|
|
break;
|
|
case 4:
|
|
istr = \"dv \";
|
|
break;
|
|
}
|
|
return (char *)mod_regno_adjust(istr,operands);
|
|
}")
|
|
|
|
;; Division for other types is straightforward.
|
|
|
|
(define_insn "divhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(div:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:HI 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
ddr r%0,r%2
|
|
dd r%0,%2 ")
|
|
|
|
(define_insn "divhf3"
|
|
[(set (match_operand:HF 0 "register_operand" "=r,r")
|
|
(div:HF (match_operand:HF 1 "register_operand" "0,0")
|
|
(match_operand:HF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
fdr r%0,r%2
|
|
fd r%0,%2 ")
|
|
|
|
(define_insn "divtqf3"
|
|
[(set (match_operand:TQF 0 "register_operand" "=r,r")
|
|
(div:TQF (match_operand:TQF 1 "register_operand" "0,0")
|
|
(match_operand:TQF 2 "general_operand" "r,m")))]
|
|
""
|
|
"@
|
|
efdr r%0,r%2
|
|
efd r%0,%2 ")
|
|
|
|
|
|
;; Other arithmetic instructions:
|
|
|
|
;; Absolute value
|
|
|
|
(define_insn "absqi2"
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
|
(abs:QI (match_operand:QI 1 "register_operand" "r")))]
|
|
""
|
|
"abs r%0,r%1")
|
|
|
|
(define_insn "abshi2"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(abs:HI (match_operand:HI 1 "register_operand" "r")))]
|
|
""
|
|
"dabs r%0,r%1")
|
|
|
|
(define_insn "abshf2"
|
|
[(set (match_operand:HF 0 "register_operand" "=r")
|
|
(abs:HF (match_operand:HF 1 "register_operand" "r")))]
|
|
""
|
|
"fabs r%0,r%1")
|
|
|
|
|
|
;; Negation
|
|
|
|
(define_insn "negqi2"
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
|
(neg:QI (match_operand:QI 1 "register_operand" "r")))]
|
|
""
|
|
"neg r%0,r%1")
|
|
|
|
(define_insn "neghi2"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(neg:HI (match_operand:HI 1 "register_operand" "r")))]
|
|
""
|
|
"dneg r%0,r%1")
|
|
|
|
(define_insn "neghf2"
|
|
[(set (match_operand:HF 0 "register_operand" "=r")
|
|
(neg:HF (match_operand:HF 1 "register_operand" "r")))]
|
|
""
|
|
"fneg r%0,r%1")
|
|
|
|
; The 1750A does not have an extended float negate instruction, so simulate.
|
|
(define_expand "negtqf2"
|
|
[(set (match_operand:TQF 0 "register_operand" "=&r")
|
|
(neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
|
|
""
|
|
"
|
|
emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
|
|
emit_insn(gen_rtx(SET,VOIDmode,operands[0],
|
|
gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
|
|
DONE;
|
|
")
|
|
|
|
|
|
;; bit-logical instructions
|
|
|
|
;; AND
|
|
|
|
(define_insn "andqi3"
|
|
[(set (match_operand:QI 0 "general_operand" "=r,r,r")
|
|
(and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
|
|
(match_operand:QI 2 "general_operand" "M,r,m")))]
|
|
""
|
|
"@
|
|
andm r%0,%2
|
|
andr r%0,r%2
|
|
and r%0,%2 ")
|
|
|
|
; This sets incorrect condition codes. See notice_update_cc()
|
|
(define_insn "andhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(and:HI (match_operand:HI 1 "register_operand" "%0")
|
|
(match_operand:HI 2 "register_operand" "r")))]
|
|
""
|
|
"danr.m %0,%2")
|
|
|
|
;; OR
|
|
|
|
(define_insn "iorqi3"
|
|
[(set (match_operand:QI 0 "general_operand" "=r,r,r")
|
|
(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
|
|
(match_operand:QI 2 "general_operand" "M,r,m")))]
|
|
""
|
|
"@
|
|
orim r%0,%2
|
|
orr r%0,r%2
|
|
or r%0,%2 ")
|
|
|
|
; This sets incorrect condition codes. See notice_update_cc()
|
|
(define_insn "iorhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(ior:HI (match_operand:HI 1 "register_operand" "%0")
|
|
(match_operand:HI 2 "register_operand" "r")))]
|
|
""
|
|
"dorr.m %0,%2")
|
|
|
|
;; XOR
|
|
|
|
(define_insn "xorqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r,r")
|
|
(xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
|
|
(match_operand:QI 2 "general_operand" "M,r,m")))]
|
|
""
|
|
"@
|
|
xorm r%0,%2
|
|
xorr r%0,r%2
|
|
xor r%0,%2 ")
|
|
|
|
; This sets incorrect condition codes. See notice_update_cc()
|
|
(define_insn "xorhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(xor:HI (match_operand:HI 1 "register_operand" "%0")
|
|
(match_operand:HI 2 "register_operand" "r")))]
|
|
""
|
|
"dxrr.m %0,%2")
|
|
|
|
;; NAND
|
|
|
|
(define_insn ""
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r,r")
|
|
(ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
|
|
(not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
|
|
""
|
|
"@
|
|
nim r%0,%2
|
|
nr r%0,r%2
|
|
n r%0,%2 ")
|
|
|
|
; This sets incorrect condition codes. See notice_update_cc()
|
|
(define_insn ""
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
|
|
(not:HI (match_operand:HI 2 "register_operand" "r"))))]
|
|
""
|
|
"dnr.m %0,%2")
|
|
|
|
;; NOT
|
|
|
|
(define_insn "one_cmplqi2"
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
|
(not:QI (match_operand:QI 1 "register_operand" "0")))]
|
|
""
|
|
"nr r%0,r%0")
|
|
|
|
; This sets incorrect condition codes. See notice_update_cc()
|
|
(define_insn "one_cmplhi2"
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
|
(not:HI (match_operand:HI 1 "register_operand" "0")))]
|
|
""
|
|
"dnr.m %0,%0")
|
|
|
|
|
|
;; Shift instructions
|
|
|
|
; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
|
|
(define_insn "ashlqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r,r")
|
|
(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0")
|
|
(match_operand:QI 2 "general_operand" "O,I,r")))]
|
|
""
|
|
"@
|
|
; optimized away an SLL r%0,0
|
|
sll r%0,%2
|
|
slr r%0,r%2 ")
|
|
|
|
(define_insn "ashlhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(ashift:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "L,r")))]
|
|
"" ; the 'L' constraint is a slight imprecise...
|
|
"@
|
|
dsll r%0,%2
|
|
dslr r%0,r%2 ")
|
|
|
|
(define_insn "lshrqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r")
|
|
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
srl r%0,%2
|
|
neg r%2,r%2\;slr r%0,r%2 ")
|
|
|
|
(define_insn "lshrhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "L,r")))]
|
|
"" ; the 'L' constraint is a slight imprecise...
|
|
"@
|
|
dsrl r%0,%2
|
|
neg r%2,r%2\;dslr r%0,r%2 ")
|
|
|
|
(define_insn "ashrqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r")
|
|
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
sra r%0,%2
|
|
neg r%2,r%2\;sar r%0,r%2 ")
|
|
|
|
(define_insn "ashrhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
dsra r%0,%2
|
|
neg r%2,r%2\;dsar r%0,r%2 ")
|
|
|
|
|
|
;; rotate instructions
|
|
|
|
(define_insn "rotlqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r")
|
|
(rotate:QI (match_operand:QI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
slc r%0,%2
|
|
scr r%0,r%2 ")
|
|
|
|
(define_insn "rotlhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(rotate:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
dslc r%0,%2
|
|
dscr r%0,r%2 ")
|
|
|
|
(define_insn "rotrqi3"
|
|
[(set (match_operand:QI 0 "register_operand" "=r,r")
|
|
(rotatert:QI (match_operand:QI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
slc r%0,%2
|
|
neg r%2,r%2\;scr r%0,r%2 ")
|
|
|
|
(define_insn "rotrhi3"
|
|
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
(rotatert:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
(match_operand:QI 2 "general_operand" "I,r")))]
|
|
""
|
|
"@
|
|
dslc r%0,%2
|
|
neg r%2,r%2\;dscr r%0,r%2 ")
|
|
|
|
|
|
|
|
;; Special cases of bit-field insns which we should
|
|
;; recognize in preference to the general case.
|
|
;; These handle aligned 8-bit and 16-bit fields,
|
|
;; which can usually be done with move instructions.
|
|
; 1750: t.b.d.
|
|
;********************
|
|
|
|
;; Bit field instructions, general cases.
|
|
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
|
|
;; so that its address is reloaded.
|
|
|
|
;; (define_insn "extv" ...
|
|
|
|
;; (define_insn "extzv" ...
|
|
|
|
;; (define_insn "insv" ...
|
|
|
|
;; Now recognize bit field insns that operate on registers
|
|
;; (or at least were intended to do so).
|
|
;[unnamed only]
|
|
|
|
;; Special patterns for optimizing bit-field instructions.
|
|
;**************************************
|
|
|
|
; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
|
|
; [(set (match_operand:QI 0 "general_operand" "=d")
|
|
; (leu (cc0) (const_int 0)))]
|
|
; ""
|
|
; "* cc_status = cc_prev_status;
|
|
; return \"sls %0\"; ")
|
|
|
|
|
|
;; Basic conditional jump instructions.
|
|
|
|
(define_insn "beq"
|
|
[(set (pc)
|
|
(if_then_else (eq (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn "bne"
|
|
[(set (pc)
|
|
(if_then_else (ne (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn "bgt"
|
|
[(set (pc)
|
|
(if_then_else (gt (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn "blt"
|
|
[(set (pc)
|
|
(if_then_else (lt (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn "bge"
|
|
[(set (pc)
|
|
(if_then_else (ge (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn "ble"
|
|
[(set (pc)
|
|
(if_then_else (le (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
|
|
; no unsigned branches available on 1750. But GCC still needs them, so faking:
|
|
|
|
(define_insn "bgtu"
|
|
[(set (pc)
|
|
(if_then_else (gtu (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"jc gt,%l0 ; Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn "bltu"
|
|
[(set (pc)
|
|
(if_then_else (ltu (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"jc lt,%l0 ; Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn "bgeu"
|
|
[(set (pc)
|
|
(if_then_else (geu (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"jc ge,%l0 ; Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn "bleu"
|
|
[(set (pc)
|
|
(if_then_else (leu (cc0)
|
|
(const_int 0))
|
|
(label_ref (match_operand 0 "" ""))
|
|
(pc)))]
|
|
""
|
|
"jc le,%l0 ; Warning: this should be an *unsigned* test!")
|
|
|
|
|
|
;; Negated conditional jump instructions.
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (eq (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (ne (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (gt (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (lt (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (ge (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (le (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
|
|
")
|
|
|
|
|
|
;; Negated unsigned conditional jump instructions (faked for 1750).
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (gtu (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (ltu (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (geu (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
|
|
|
|
(define_insn ""
|
|
[(set (pc)
|
|
(if_then_else (leu (cc0)
|
|
(const_int 0))
|
|
(pc)
|
|
(label_ref (match_operand 0 "" ""))))]
|
|
""
|
|
"jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
|
|
|
|
;; Tablejump
|
|
;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
|
|
(define_insn "tablejump"
|
|
[(set (pc)
|
|
(match_operand:QI 0 "register_operand" "b"))
|
|
(use (label_ref (match_operand 1 "" "")))]
|
|
""
|
|
"jc 15,0,r%0 ; tablejump label_ref=%1")
|
|
|
|
|
|
;; Unconditional jump
|
|
(define_insn "jump"
|
|
[(set (pc)
|
|
(label_ref (match_operand 0 "" "")))]
|
|
""
|
|
"jc uc,%0")
|
|
|
|
;; Call subroutine, returning value in operand 0
|
|
;; (which must be a hard register).
|
|
(define_insn "call_value"
|
|
[(set (match_operand 0 "register_operand" "r")
|
|
(call (match_operand:QI 1 "memory_operand" "m")
|
|
(match_operand:QI 2 "general_operand" "g")))]
|
|
;; Operand 2 not really used for 1750.
|
|
""
|
|
"sjs r15,%1 ; return value in R0")
|
|
|
|
;; Call subroutine with no return value.
|
|
|
|
;; Operand 1 not really used in MIL-STD-1750.
|
|
(define_insn ""
|
|
[(call (match_operand:QI 0 "memory_operand" "mp")
|
|
(match_operand:QI 1 "general_operand" ""))]
|
|
""
|
|
"sjs r15,%0 ; no return value")
|
|
|
|
;;;;;;;;;;;; 1750: NOT READY YET.
|
|
(define_insn "call"
|
|
[(call (match_operand:QI 0 "" "")
|
|
(match_operand:QI 1 "" ""))]
|
|
""
|
|
"ANYCALL %0")
|
|
|
|
|
|
; (define_insn "return"
|
|
; [(return)]
|
|
; ""
|
|
; "*
|
|
; {
|
|
; rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
|
|
; output_asm_insn(\"ret.m %0\",&oprnd);
|
|
; return \"\;\";
|
|
; } ")
|
|
|
|
(define_insn "indirect_jump"
|
|
[(set (pc) (match_operand:QI 0 "address_operand" "p"))]
|
|
""
|
|
"jci 15,%0")
|
|
|
|
(define_insn "nop"
|
|
[(const_int 0)]
|
|
""
|
|
"nop")
|
|
|
|
|
|
;; Subtract One and Jump (if non-zero)
|
|
(define_peephole
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
|
(plus:QI (match_operand:QI 1 "register_operand" "%0")
|
|
(match_operand:QI 2 "immediate_operand" "J")))
|
|
(set (cc0) (match_dup 0))
|
|
(set (pc)
|
|
(if_then_else (ne (cc0) (const_int 0))
|
|
(label_ref (match_operand 3 "" ""))
|
|
(pc)))
|
|
]
|
|
"INTVAL(operands[2]) == -1"
|
|
"soj r%0,%3")
|
|
|
|
;;;End.
|
|
|