729 lines
16 KiB
C
729 lines
16 KiB
C
/* Subroutines for assembler code output on the NS32000.
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Copyright (C) 1988 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Some output-actions in ns32k.md need these. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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#ifdef OSF_OS
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int ns32k_num_files = 0;
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#endif
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void
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trace (s, s1, s2)
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char *s, *s1, *s2;
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{
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fprintf (stderr, s, s1, s2);
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}
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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int
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hard_regno_mode_ok( regno, mode )
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int regno;
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int mode;
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{
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switch( mode ) {
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case QImode:
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case HImode:
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case PSImode:
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case SImode:
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case PDImode:
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case VOIDmode:
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case BLKmode:
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if( (regno < 8) || (regno == 16) || (regno == 17) ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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case DImode:
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if( (regno < 8) && ((regno & 1) == 0) ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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case SFmode:
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case SCmode:
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if( TARGET_32081 ) {
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if( regno < 16 ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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}
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else {
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if( regno < 8 ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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}
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case DFmode:
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case DCmode:
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if( (regno & 1) == 0 ) {
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if( TARGET_32081 ) {
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if( regno < 16 ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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}
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else {
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if( regno < 8 ) {
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return( 1 );
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}
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else {
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return( 0 );
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}
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}
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}
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else {
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return( 0 );
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}
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case XFmode:
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abort( 0 );
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case CCmode:
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abort( 0 );
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case TImode:
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abort( 0 );
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case XCmode:
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abort( 0 );
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case TFmode:
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abort( 0 );
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case TCmode:
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abort( 0 );
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default:
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fprintf( stderr, "cant match mode %d\n", mode );
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abort( 0 );
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}
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abort(0);
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}
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/* ADDRESS_COST calls this. This function is not optimal
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for the 32032 & 32332, but it probably is better than
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the default. */
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int
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calc_address_cost (operand)
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rtx operand;
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{
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int i;
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int cost = 0;
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if (GET_CODE (operand) == MEM)
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cost += 3;
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if (GET_CODE (operand) == MULT)
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cost += 2;
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#if 0
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if (GET_CODE (operand) == REG)
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cost += 1; /* not really, but the documentation
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says different amount of registers
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shouldn't return the same costs */
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#endif
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switch (GET_CODE (operand))
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{
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case REG:
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case CONST:
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case CONST_INT:
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case CONST_DOUBLE:
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case SYMBOL_REF:
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case LABEL_REF:
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case POST_DEC:
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case PRE_DEC:
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break;
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case MULT:
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case MEM:
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case PLUS:
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for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
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{
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cost += calc_address_cost (XEXP (operand, i));
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}
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default:
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break;
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}
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return cost;
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}
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/* Return the register class of a scratch register needed to copy IN into
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or out of a register in CLASS in MODE. If it can be done directly,
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NO_REGS is returned. */
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enum reg_class
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secondary_reload_class (class, mode, in)
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enum reg_class class;
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enum machine_mode mode;
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rtx in;
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{
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int regno = true_regnum (in);
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if (regno >= FIRST_PSEUDO_REGISTER)
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regno = -1;
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/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
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into anything. */
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if (class == GENERAL_REGS || (regno >= 0 && regno < 8))
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return NO_REGS;
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/* Constants, memory, and FP registers can go into FP registers */
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if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS))
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return NO_REGS;
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/* Otherwise, we need GENERAL_REGS. */
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return GENERAL_REGS;
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}
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/* Generate the rtx that comes from an address expression in the md file */
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/* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
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scale must be converted from an exponent (from ASHIFT) to a
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multiplier (for MULT). */
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rtx
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gen_indexed_expr (base, index, scale)
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rtx base, index, scale;
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{
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rtx addr;
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/* This generates an illegal addressing mode, if BASE is
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fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */
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if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
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base = gen_rtx (MEM, SImode, base);
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addr = gen_rtx (MULT, SImode, index,
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gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale)));
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addr = gen_rtx (PLUS, SImode, base, addr);
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return addr;
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}
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/* Return 1 if OP is a valid operand of mode MODE. This
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predicate rejects operands which do not have a mode
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(such as CONST_INT which are VOIDmode). */
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int
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reg_or_mem_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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return (GET_MODE (op) == mode
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&& (GET_CODE (op) == REG
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|| GET_CODE (op) == SUBREG
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|| GET_CODE (op) == MEM));
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}
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/* Return the best assembler insn template
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for moving operands[1] into operands[0] as a fullword. */
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static char *
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singlemove_string (operands)
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rtx *operands;
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{
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if (GET_CODE (operands[1]) == CONST_INT
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&& INTVAL (operands[1]) <= 7
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&& INTVAL (operands[1]) >= -8)
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return "movqd %1,%0";
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return "movd %1,%0";
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}
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char *
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output_move_double (operands)
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rtx *operands;
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{
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enum anon1 { REGOP, OFFSOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
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rtx latehalf[2];
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/* First classify both operands. */
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if (REG_P (operands[0]))
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optype0 = REGOP;
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else if (offsettable_memref_p (operands[0]))
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optype0 = OFFSOP;
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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optype0 = POPOP;
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else
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optype0 = RNDOP;
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if (REG_P (operands[1]))
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optype1 = REGOP;
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else if (CONSTANT_ADDRESS_P (operands[1])
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|| GET_CODE (operands[1]) == CONST_DOUBLE)
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optype1 = CNSTOP;
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else if (offsettable_memref_p (operands[1]))
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optype1 = OFFSOP;
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else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
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optype1 = POPOP;
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else
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optype1 = RNDOP;
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/* Check for the cases that the operand constraints are not
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supposed to allow to happen. Abort if we get one,
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because generating code for these cases is painful. */
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if (optype0 == RNDOP || optype1 == RNDOP)
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abort ();
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/* Ok, we can do one word at a time.
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Normally we do the low-numbered word first,
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but if either operand is autodecrementing then we
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do the high-numbered word first.
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In either case, set up in LATEHALF the operands to use
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for the high-numbered word and in some cases alter the
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operands in OPERANDS to be suitable for the low-numbered word. */
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if (optype0 == REGOP)
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latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (optype0 == OFFSOP)
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latehalf[0] = adj_offsettable_operand (operands[0], 4);
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else
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latehalf[0] = operands[0];
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if (optype1 == REGOP)
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latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else if (optype1 == OFFSOP)
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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else if (optype1 == CNSTOP)
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{
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if (CONSTANT_ADDRESS_P (operands[1]))
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latehalf[1] = const0_rtx;
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else if (GET_CODE (operands[1]) == CONST_DOUBLE)
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split_double (operands[1], &operands[1], &latehalf[1]);
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}
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else
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latehalf[1] = operands[1];
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/* If one or both operands autodecrementing,
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do the two words, high-numbered first. */
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if (optype0 == POPOP || optype1 == POPOP)
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{
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output_asm_insn (singlemove_string (latehalf), latehalf);
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return singlemove_string (operands);
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}
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/* Not autodecrementing. Do the two words, low-numbered first. */
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output_asm_insn (singlemove_string (operands), operands);
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operands[0] = latehalf[0];
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operands[1] = latehalf[1];
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return singlemove_string (operands);
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}
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int
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check_reg (oper, reg)
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rtx oper;
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int reg;
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{
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register int i;
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if (oper == 0)
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return 0;
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switch (GET_CODE(oper))
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{
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case REG:
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return (REGNO(oper) == reg) ? 1 : 0;
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case MEM:
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return check_reg(XEXP(oper, 0), reg);
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case PLUS:
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case MULT:
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return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg);
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}
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return 0;
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}
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/* PRINT_OPERAND is defined to call this function,
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which is easier to debug than putting all the code in
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a macro definition in ns32k.h. */
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void
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print_operand (file, x, code)
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FILE *file;
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rtx x;
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char code;
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{
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if (code == '$')
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PUT_IMMEDIATE_PREFIX (file);
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else if (code == '?')
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PUT_EXTERNAL_PREFIX (file);
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else if (GET_CODE (x) == REG)
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fprintf (file, "%s", reg_names[REGNO (x)]);
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else if (GET_CODE (x) == MEM)
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{
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rtx tmp = XEXP (x, 0);
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#if ! (defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC))
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if (GET_CODE (tmp) != CONST_INT)
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{
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char *out = XSTR (tmp, 0);
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if (out[0] == '*')
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{
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PUT_ABSOLUTE_PREFIX (file);
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fprintf (file, "%s", &out[1]);
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}
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else
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ASM_OUTPUT_LABELREF (file, out);
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}
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else
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#endif
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output_address (XEXP (x, 0));
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}
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else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode)
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{
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if (GET_MODE (x) == DFmode)
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX(file);
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#ifdef SEQUENT_ASM
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/* Sequent likes it's floating point constants as integers */
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fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
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#else
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#ifdef ENCORE_ASM
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fprintf (file, "0f%.20e", u.d);
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#else
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fprintf (file, "0d%.20e", u.d);
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#endif
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#endif
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}
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else
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX (file);
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#ifdef SEQUENT_ASM
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/* We have no way of winning if we can't get the bits
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for a sequent floating point number. */
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#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
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abort ();
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#endif
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{
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union { float f; long l; } uu;
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uu.f = u.d;
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fprintf (file, "0Fx%08x", uu.l);
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}
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#else
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fprintf (file, "0f%.20e", u.d);
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#endif
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}
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}
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else
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{
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#ifndef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
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if (GET_CODE (x) == CONST_INT)
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#endif
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PUT_IMMEDIATE_PREFIX(file);
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output_addr_const (file, x);
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}
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}
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/* PRINT_OPERAND_ADDRESS is defined to call this function,
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which is easier to debug than putting all the code in
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a macro definition in ns32k.h . */
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/* Completely rewritten to get this to work with Gas for PC532 Mach.
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This function didn't work and I just wasn't able (nor very willing) to
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figure out how it worked.
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90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
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print_operand_address (file, addr)
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register FILE *file;
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register rtx addr;
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{
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static char scales[] = { 'b', 'w', 'd', 0, 'q', };
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rtx offset, base, indexexp, tmp;
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int scale;
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if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
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{
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fprintf (file, "tos");
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return;
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}
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offset = NULL;
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base = NULL;
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indexexp = NULL;
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while (addr != NULL)
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{
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if (GET_CODE (addr) == PLUS)
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{
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if (GET_CODE (XEXP (addr, 0)) == PLUS)
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{
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tmp = XEXP (addr, 1);
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addr = XEXP (addr, 0);
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}
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else
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{
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tmp = XEXP (addr,0);
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addr = XEXP (addr,1);
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}
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}
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else
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{
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tmp = addr;
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addr = NULL;
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}
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switch (GET_CODE (tmp))
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{
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case PLUS:
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abort ();
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case MEM:
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if (base)
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{
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indexexp = base;
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base = tmp;
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}
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else
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base = tmp;
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break;
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case REG:
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if (REGNO (tmp) < 8)
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if (base)
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{
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indexexp = tmp;
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}
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else
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base = tmp;
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else
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if (base)
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{
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indexexp = base;
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base = tmp;
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}
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else
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base = tmp;
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break;
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case MULT:
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indexexp = tmp;
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break;
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case CONST:
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case CONST_INT:
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case SYMBOL_REF:
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case LABEL_REF:
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if (offset)
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offset = gen_rtx (PLUS, SImode, tmp, offset);
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else
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offset = tmp;
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break;
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default:
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abort ();
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}
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}
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if (! offset)
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offset = const0_rtx;
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#ifdef INDEX_RATHER_THAN_BASE
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/* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */
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if (base && !indexexp && GET_CODE (base) == REG
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&& REG_OK_FOR_INDEX_P (REGNO (base))
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{
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indexexp = base;
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base = 0;
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}
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#endif
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/* now, offset, base and indexexp are set */
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if (! base)
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{
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#if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
|
||
if (GET_CODE (offset) == CONST_INT)
|
||
/* if (! (GET_CODE (offset) == LABEL_REF
|
||
|| GET_CODE (offset) == SYMBOL_REF)) */
|
||
#endif
|
||
PUT_ABSOLUTE_PREFIX (file);
|
||
}
|
||
|
||
output_addr_const (file, offset);
|
||
if (base) /* base can be (REG ...) or (MEM ...) */
|
||
switch (GET_CODE (base))
|
||
{
|
||
/* now we must output base. Possible alternatives are:
|
||
(rN) (REG ...)
|
||
(sp) (REG ...)
|
||
(fp) (REG ...)
|
||
(pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output
|
||
(disp(fp)) (MEM ...) just before possible [rX:y]
|
||
(disp(sp)) (MEM ...)
|
||
(disp(sb)) (MEM ...)
|
||
*/
|
||
case REG:
|
||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||
break;
|
||
case MEM:
|
||
addr = XEXP(base,0);
|
||
base = NULL;
|
||
offset = NULL;
|
||
while (addr != NULL)
|
||
{
|
||
if (GET_CODE (addr) == PLUS)
|
||
{
|
||
if (GET_CODE (XEXP (addr, 0)) == PLUS)
|
||
{
|
||
tmp = XEXP (addr, 1);
|
||
addr = XEXP (addr, 0);
|
||
}
|
||
else
|
||
{
|
||
tmp = XEXP (addr, 0);
|
||
addr = XEXP (addr, 1);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
tmp = addr;
|
||
addr = NULL;
|
||
}
|
||
switch (GET_CODE (tmp))
|
||
{
|
||
case REG:
|
||
base = tmp;
|
||
break;
|
||
case CONST:
|
||
case CONST_INT:
|
||
case SYMBOL_REF:
|
||
case LABEL_REF:
|
||
if (offset)
|
||
offset = gen_rtx (PLUS, SImode, tmp, offset);
|
||
else
|
||
offset = tmp;
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
if (! offset)
|
||
offset = const0_rtx;
|
||
fprintf (file, "(");
|
||
output_addr_const (file, offset);
|
||
if (base)
|
||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||
#ifdef BASE_REG_NEEDED
|
||
else if (TARGET_SB)
|
||
fprintf (file, "(sb)");
|
||
else
|
||
abort ();
|
||
#endif
|
||
fprintf (file, ")");
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
#ifdef PC_RELATIVE
|
||
else /* no base */
|
||
if (GET_CODE (offset) == LABEL_REF || GET_CODE (offset) == SYMBOL_REF)
|
||
fprintf (file, "(pc)");
|
||
#endif
|
||
#ifdef BASE_REG_NEEDED /* this is defined if the assembler always
|
||
needs a base register */
|
||
else if (TARGET_SB)
|
||
fprintf (file, "(sb)");
|
||
else
|
||
abort ();
|
||
#endif
|
||
/* now print index if we have one */
|
||
if (indexexp)
|
||
{
|
||
if (GET_CODE (indexexp) == MULT)
|
||
{
|
||
scale = INTVAL (XEXP (indexexp, 1)) >> 1;
|
||
indexexp = XEXP (indexexp, 0);
|
||
}
|
||
else
|
||
scale = 0;
|
||
if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8)
|
||
abort ();
|
||
|
||
#ifdef UTEK_ASM
|
||
fprintf (file, "[%c`%s]",
|
||
scales[scale],
|
||
reg_names[REGNO (indexexp)]);
|
||
#else
|
||
fprintf (file, "[%s:%c]",
|
||
reg_names[REGNO (indexexp)],
|
||
scales[scale]);
|
||
#endif
|
||
}
|
||
}
|
||
|
||
/* National 32032 shifting is so bad that we can get
|
||
better performance in many common cases by using other
|
||
techniques. */
|
||
char *
|
||
output_shift_insn (operands)
|
||
rtx *operands;
|
||
{
|
||
if (GET_CODE (operands[2]) == CONST_INT
|
||
&& INTVAL (operands[2]) > 0
|
||
&& INTVAL (operands[2]) <= 3)
|
||
if (GET_CODE (operands[0]) == REG)
|
||
{
|
||
if (GET_CODE (operands[1]) == REG)
|
||
{
|
||
if (REGNO (operands[0]) == REGNO (operands[1]))
|
||
{
|
||
if (operands[2] == const1_rtx)
|
||
return "addd %0,%0";
|
||
else if (INTVAL (operands[2]) == 2)
|
||
return "addd %0,%0\n\taddd %0,%0";
|
||
}
|
||
if (operands[2] == const1_rtx)
|
||
return "movd %1,%0\n\taddd %0,%0";
|
||
|
||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||
return "addr %a1,%0";
|
||
}
|
||
if (operands[2] == const1_rtx)
|
||
return "movd %1,%0\n\taddd %0,%0";
|
||
}
|
||
else if (GET_CODE (operands[1]) == REG)
|
||
{
|
||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||
return "addr %a1,%0";
|
||
}
|
||
else if (INTVAL (operands[2]) == 1
|
||
&& GET_CODE (operands[1]) == MEM
|
||
&& rtx_equal_p (operands [0], operands[1]))
|
||
{
|
||
rtx temp = XEXP (operands[1], 0);
|
||
|
||
if (GET_CODE (temp) == REG
|
||
|| (GET_CODE (temp) == PLUS
|
||
&& GET_CODE (XEXP (temp, 0)) == REG
|
||
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
|
||
return "addd %0,%0";
|
||
}
|
||
else return "ashd %2,%0";
|
||
return "ashd %2,%0";
|
||
}
|