MatCat.OpenSource/8sa1-binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
104,201 Commits 1 Branch 0 Tags 383 MiB
c2137f55ad
Commit Graph

994 Commits

Author SHA1 Message Date
Nelson Chu
c2137f55ad RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. 
https://github.com/riscv/riscv-asm-manual/pull/61

We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
and zext.w.  In a certain sense, zext.b is not a pseudo - It is an
alias of andi.  Similarly, sext.b and sext.h are aliases of other
rvb instructions, when we enable b extension; But they are pseudos
when we just enable rvi.  However, this patch does not consider the
rvb cases.  Besides, zext.w is only valid in rv64.

gas/
    * config/tc-riscv.c (riscv_ext): New function.  Use md_assemblef
    to expand the zext and sext pseudos, to give them a chance to be
    expanded into c-ext instructions.
    (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
    * testsuite/gas/riscv/ext.s: New testcase.
    * testsuite/gas/riscv/ext-32.d: Likewise.
    * testsuite/gas/riscv/ext-64.d: Likewise.
include/
    * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
 2020-12-10 10:50:44 +08:00
Nelson Chu
729a53530e RISC-V: Control fence.i and csr instructions by zifencei and zicsr. 
bfd/
    * elfxx-riscv.c (riscv_ext_dont_care_version): New function.  Return
    TRUE if we don't care the versions of the extensions.  These extensions
    are added to the subset list for special purposes, with the explicit
    versions or the RISCV_UNKNOWN_VERSION versions.
    (riscv_parse_add_subset): If we do care the versions of the extension,
    and the versions are unknown, then report errors for the non-implicit
    extensions, and return directly for the implicit one.
    (riscv_arch_str1): Do not output i extension after e, and the extensions
    which versions are unknown.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
    and INSN_CLASS_ZIFENCEI.
    * testsuite/gas/riscv/march-imply-i.s: New testcase.
    * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase.  The version
    of i is less than 2.1, and zi* are supported in the chosen spec, so
    enable the fence.i and csr instructions, also output the implicit zi* to
    the arch string.
    * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
    not supported in the spec 2.2.  Enable the related instructions since
    i's version is less than 2.1, but do not output them.
    * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase.  The version
    of i is 2.1, so don't add it's implicit zi*, and disable the related
    instructions.
    * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
    * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
    explicitly, so enable the related instructions.
    * testsuite/gas/riscv/march-imply-i2p0.d: Removed.
    * testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
    * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
    * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
    zifencei and zicsr.
 2020-12-10 10:37:43 +08:00
Nelson Chu
00d4d1b0a3 RISC-V: Support to add implicit extensions for G. 
G is a special case, consider the ISA spec github issue as follows,
https://github.com/riscv/riscv-isa-manual/issues/575

My understand is that - i, m, a, f and d extensions are not g's implicit
extensions, they are g's expansions.  The zifencei is the implicit extension
of g, and so is zicsr, since it is implicited by f (or i2p1).  However,
we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
will not output to the arch string, it is only used to check what implicit
extensions are need to be added.

	bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
	RISCV_UNKNOWN_VERSION versions.
	(riscv_parse_std_ext): Add g to the subset list, we only use it
	to add the implicit extensions, but won't output it to arch string.
	(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
	for g extension.
	(riscv_arch_str1): Do not output g to the arch string.
	* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.

	gas/
	* testsuite/gas/riscv/attribute-10.d: Updated.
	* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
	* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
	are not supported in the ISA spec v2.2, so don't add and output them.

	include/
	* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
 2020-12-01 15:23:02 +08:00
Nelson Chu
7ef19aa616 RISC-V: Improve the version parsing for arch string. 
Keep the riscv_add_subset to do the same thing, and use a new
function, riscv_parse_add_subset, to cover most of the things
when parsing, including find the default versions for extensions,
and check whether the versions are valid.  The version 0p0 should
be an invalid version, that is the mistake I made before.  This
patch clarify the version rules as follows,

* We accept any version of extensions set by users, except 0p0.
* The non-standard x extensions must be set with versions in arch string.
* If user don't set the versions, or set 0p0 for the extensions, then try
  to find the supported versions according to the chosen ISA spec.
  Otherwise, report errors rather than output 0p0 for them.

Besides, we use as_bad rather than as_fatal to report more errors
for assembler.

	bfd/
	* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
	(riscv_add_subset): Likewise.
	(riscv_release_subset_list): Likewise.
	(riscv_parse_add_subset): New function.  Find and check the
	versions before adding them by riscv_add_subset.
	(riscv_parsing_subset_version): Remove use_default_version
	and change the version type from unsigned to int.  Set the
	versions to RISCV_UNKNOWN_VERSION if we can not find them
	in the arch string.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_prefixed_ext): Updated.  Since we use as_bad
	rather than as_fatal to report more errors, return NULL
	string if the parsed end_of_version is NULL, too.
	(riscv_parse_subset): Use a new boolean, no_conflict, to
	report more errors when we have more than one ISA conflicts.

	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
	RISCV_UNKNOWN_VERSION.
	(riscv_lookup_subset_version): Removed.
	(riscv_parse_subset_t): Updated.

	gas/
	* config/tc-riscv.c (riscv_get_default_ext_version):
	Change the version type from unsigned to int.
	(riscv_set_arch): Use as_bad rather than as_fatal to
	report more errors.

	* testsuite/gas/riscv/attribute-02.d: Updated since x must be
	set with versions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
	in the spec 2.2, so choose the newer spec.
	* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
	* testsuite/gas/riscv/march-fail-version.l: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.

	include/
	* opcode/riscv.h (riscv_ext_version):
	Change the version type from unsigned to int.
 2020-12-01 15:16:25 +08:00
Przemyslaw Wirkus
e64441b14c aarch64: Extract Condition flag manipulation feature from Armv8.4-A 
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A.
Please note that FLAGM stays a Armv8.4-A feature but now can be
assigned to other architectures or CPUs.

New -march option +flagm is added to enable independently this
feature.
 2020-11-16 21:07:17 +00:00
Spencer E. Olson
9372689d72 Add support for the LMBD (left-most bit detect) instruction to the PRU assembler. 
include	* opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas 	* testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
 	* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
 2020-11-09 12:41:09 +00:00
Przemyslaw Wirkus
8edca81ece aarch64: Limit Rt register number for LS64 load/store instructions 
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):

    if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;

This patch adds check if Rt fulfills above requirement.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i
 2020-11-09 11:19:44 +00:00
Przemyslaw Wirkus
af1bd771fc aarch64: Extract Pointer Authentication feature from Armv8.3-A 
Extract PAC (Pointer Authentication) feature from Armv8.3-A.
Please note that PAC stays a Armv8.3-A feature but now can be
assigned to other architectures or CPUs.
 2020-11-06 13:14:14 +00:00
Przemyslaw Wirkus
55cc012834 aarch64: Update feature RAS system registers 
This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.

Please note that early Armv8-A architectures do not officially support RAS
extension.

Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.

The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.

RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.

For details see [0].

[0] https://developer.arm.com/docs/ddi0595/i/
 2020-11-04 20:54:13 +00:00
Przemyslaw Wirkus
fd65497db4 [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7 
Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.

This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i
 2020-11-03 14:29:31 +00:00
Przemyslaw Wirkus
dd4a72c859 aarch64: Add CSR PDEC instruction 
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.

Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.

CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.

gas/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Update docs.
	* config/tc-aarch64.c (parse_csr_operand): New operand parser.
	(parse_operands): Call to CSR operand parser.
	* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
	* testsuite/gas/aarch64/csre_csr.d: New test.
	* testsuite/gas/aarch64/csre_csr.s: New test.

include/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
	(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.

opcodes/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
	* aarch64-tbl.h (CSRE): New CSRE feature handler.
	(_CSRE_INSN): New CSRE instruction type.
	(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
 2020-10-28 14:19:42 +00:00
Przemyslaw Wirkus
fd195909ce aarch64: Add DSB instruction Armv8.7-a variant 
This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.

DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:

	DSB SYnXS|#28
	DSB ISHnXS|#24
	DSB NSHnXS|#20
	DSB OSHnXS|#16

Please note that till now,  for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:

		CRm<3:2>  #imm
		  00       16
		  01       20
		  10       24
		  11       28

This patch extends current AArch64 barrier instructions with above mapping.

Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.

For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].

	[0]: https://developer.arm.com/docs/ddi0596/i

gas/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Docs update.
	* config/tc-aarch64.c (parse_operands): Add
	AARCH64_OPND_BARRIER_DSB_NXS handler.
	(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
	aarch64_barrier_opt_hsh hash.
	* testsuite/gas/aarch64/system-4-invalid.d: New test.
	* testsuite/gas/aarch64/system-4-invalid.l: New test.
	* testsuite/gas/aarch64/system-4-invalid.s: New test.
	* testsuite/gas/aarch64/system-4.d: New test.
	* testsuite/gas/aarch64/system-4.s: New test.

include/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_BARRIER_DSB_NXS.
	(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.

opcodes/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
	* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
	ins_barrier_dsb_nx.
	* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
	* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
	ext_barrier_dsb_nx.
	* aarch64-opc.c (aarch64_print_operand): New options table
	aarch64_barrier_dsb_nxs_options.
	* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
	* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
	Armv8.7-a instruction.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
 2020-10-28 14:05:05 +00:00
Przemyslaw Wirkus
8926e54e3a aarch64: Add basic support for armv8.7-a architecture 
This patch adds support for AArch64 -march=armv8.7-a command line option
in GAS.

Please note that this change ONLY extends -march= command line interface
with a new "armv8.7-a" option. Architectural changes like new instructions
will be added in following patches.

gas/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Docs update.
	* config/tc-aarch64.c (armv8.7-a): New arch.
	* doc/c-aarch64.texi (-march=armv8.7-a): Update docs.

include/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
	(AARCH64_ARCH_V8_7): New arch feature set.

opcodes/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-tbl.h (ARMV8_7): New macro.
 2020-10-28 13:58:17 +00:00
Cooper Qu
9d1ccf22fd CSKY: Add version flag in eflag and fix bug in disassembling register. 
gas/
	* config/tc-csky.c (md_begin): Add version flag in eflag.

include/
	* opcode/csky.h (CSKY_VERSION_V1): Define, currently used.
	(CSKY_VERSION_V2): Define.
	(CSKY_VERSION_V3): Define.

Change-Id: Iafe3a9ce6fe544880a225b9fae439275a828bb34
 2020-10-26 16:20:10 +08:00
Cooper Qu
548f527578 CSKY: Change ISA flag's type to bfd_uint64_t and fix build error. 
The previous patch missed one modification.
Following is the error message:
gas/config/tc-csky.c:806:5: error: 'CSKY_ARCH_804' undeclared here
(not in a function); did you mean 'CSKY_ARCH_807'?

include/
	* opcode/csky.h (CSKYV1_ISA_E1): Convert to bfd_uint64_t type.
	(CSKYV2_ISA_E1): Likewise.
	(CSKYV2_ISA_1E2): Likewise.
	(CSKYV2_ISA_2E3): Likewise.
	(CSKYV2_ISA_3E7): Likewise.
	(CSKYV2_ISA_7E10): Likewise.
	(CSKYV2_ISA_3E3R1): Likewise.
	(CSKYV2_ISA_3E3R2): Likewise.
	(CSKYV2_ISA_10E60): Likewise.
	(CSKYV2_ISA_3E3R3): Likewise.
	(CSKY_ISA_TRUST): Likewise.
	(CSKY_ISA_CACHE): Likewise.
	(CSKY_ISA_NVIC): Likewise.
	(CSKY_ISA_CP): Likewise.
	(CSKY_ISA_MP): Likewise.
	(CSKY_ISA_MP_1E2): Likewise.
	(CSKY_ISA_JAVA): Likewise.
	(CSKY_ISA_MAC): Likewise.
	(CSKY_ISA_MAC_DSP): Likewise.
	(CSKY_ISA_DSP): Likewise.
	(CSKY_ISA_DSP_1E2): Likewise.
	(CSKY_ISA_DSP_ENHANCE): Likewise.
	(CSKY_ISA_DSPE60): Likewise.
	(CSKY_ISA_FLOAT_E1): Likewise.
	(CSKY_ISA_FLOAT_1E2): Likewise.
	(CSKY_ISA_FLOAT_1E3): Likewise.
	(CSKY_ISA_FLOAT_3E4): Likewise.
	(CSKY_ISA_FLOAT_7E60): Likewise.
	(CSKY_ISA_VDSP): Likewise.
	(CSKY_ISA_VDSP_2): Likewise.
	(CSKY_ARCH_804): Define.
	(CSKY_ARCH_805): Define.
	(CSKY_ARCH_800): Define.
 2020-09-12 00:56:01 +08:00
Nick Clifton
0332f66274 Fix compile time warnings when building for the CSKY target on a 32-bit host. 
incldue	* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for
	this value.

opcodes	* csky-dis.c (csky_output_operand): Coerce the immediate values to
	long before printing.
 2020-09-10 09:58:15 +01:00
Cooper Qu
6a1ed9106f CSKY: Change mvtc and mulsw's ISA flag. 
gas/
	* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
	(CSKY_ISA_860): Likewise.

include/
	* opcode/csky.h (CSKY_ISA_DSPE60): Define.

opcodes/
	* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
	ISA flag.
 2020-09-09 19:26:34 +08:00
Cooper Qu
1feede9b38 CSKY: Add FPUV3 instructions, which supported by ck860f. 
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>

gas/
	* config/tc-csky.c (float_work_fpuv3_fmovi): New function,
	helper function to encode fpuv3 fmovi instructions.
	(float_work_fpuv3_fstore): New function.
	(struct literal): Add new member 'offset'.
	(csky_cpus): New cpu CK860f.
	(enter_literal): Return literal pool pointer instead of offset.
	(parse_rt): Adjust the change of enter_literal.
	(parse_rtf): Likewise.
	(v1_work_lrw): Likewise.
	(v1_work_jbsr): Likewise.
	(v2_work_lrw): Likewise.
	(v2_work_jbsr): Likewise.
	(v2_work_jsri): Likewise.
	(vdsp_work_vlrw): Likewise.
	(is_freglist_legal): Add handler for FPUV3.
	(parse_type_freg): Likewise.
	(is_imm_within_range): Set e.X_add_number if it is a signed and
	negtive number.
	(get_operand_value): Add handler for OPRND_TYPE_IMM9b,
	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI
	and OPRND_TYPE_DFLOAT_FMOVI.
	(float_to_half): Convert float number to harf float.

opcodes/
	* csky-dis.c (csky_output_operand): Add handlers for
	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
	OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
	to support FPUV3 instructions.
	* csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
	OPRND_TYPE_DFLOAT_FMOVI.
	(OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
	 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
	 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
	 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
	 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
	 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
	 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
	 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
	 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
	 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
	 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
	 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
	 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
	(csky_v2_opcodes): Add FPUV3 instructions.

include/
	* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
 2020-09-09 19:25:40 +08:00
Alex Coplan
38cf07a6c0 aarch64: Add support for Armv8-R system registers 
This patch adds support for the system registers introduced in Armv8-R
AArch64.

gas/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
	validation function.
	(parse_sys_ins_reg): Likewise.
	(print_operands): Pass CPU features to aarch64_print_operand().
	* testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
	* testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
	* testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
	* testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
	* testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
	* testsuite/gas/aarch64/v8-r-sysregs.d: New test.
	* testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.

include/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take
	system register name in order to simplify validation for v8-R.
	(aarch64_print_operand): Also take CPU feature set, as disassembly for
	system registers now depends on arch variant.

opcodes/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-dis.c (print_operands): Pass CPU features to
	aarch64_print_operand().
	* aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
	preferred disassembly of system registers.
	(SR_RNG): Refactor to use new SR_FEAT2 macro.
	(SR_FEAT2): New.
	(SR_V8_1_A): New.
	(SR_V8_4_A): New.
	(SR_V8_A): New.
	(SR_V8_R): New.
	(SR_EXPAND_ELx): New.
	(SR_EXPAND_EL12): New.
	(aarch64_sys_regs): Specify which registers are only on
	A-profile, add R-profile system registers.
	(ENC_BARLAR): New.
	(PRBARn_ELx): New.
	(PRLARn_ELx): New.
	(aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
	Armv8-R AArch64.
 2020-09-08 14:21:44 +01:00
Alex Coplan
95830c988a aarch64: Add base support for Armv8-R 
This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.

The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.

The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.

bfd/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* archures.c (bfd_mach_aarch64_8R): New.
	* bfd-in2.h: Regenerate.
	* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
	(bfd_aarch64_arch_ilp32): Update tail pointer.

gas/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
	* doc/c-aarch64.texi: Document -march=armv8-r.

include/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
	(AARCH64_FEATURE_V8_R): New.
	(AARCH64_ARCH_V8): Include new A-profile feature bit.
	(AARCH64_ARCH_V8_R): New.

opcodes/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-dis.c (arch_variant): New.
	(determine_disassembling_preference): Disassemble according to
	arch variant.
	(select_aarch64_variant): New.
	(print_insn_aarch64): Set feature set.
 2020-09-08 14:14:11 +01:00
Alan Modra
7c80dd4c2c ubsan: v850-opc.c:412 left shift cannot be represented 
include/
	* opcode/v850.h (struct v850_operand <insert>): Make param op an
	unsigned long.
opcodes/
	* v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
	(insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
	(insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
	(insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
	(insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
	(insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
	(nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
	for value parameter and update code to suit.
	(extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
	(extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 2020-09-02 16:30:44 +09:30
Cooper Qu
4211a34001 CSKY: Add CPU CK803r3. 
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.

gas/
	* config/tc-csky.c (csky_cpus): Add ck803r3.
	(CSKY_ISA_803R3): Define.
	(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.

include/
	* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.

opcodes/
	* csky-opc.h (csky_v2_opcodes): Move divul and divsl
	to CSKYV2_ISA_3E3R3 instruction set.
 2020-09-02 14:21:31 +08:00
Alan Modra
1174d92070 PR26493 UBSAN: elfnn-riscv.c left shift of negative value 
include/
	PR 26493
	* opcode/riscv.h (OP_MASK_CSR, OP_MASK_CUSTOM_IMM)
	(OP_MASK_FUNCT7, OP_MASK_RS3): Make unsigned.
bfd/
	PR 26493
	* elfnn-riscv.c (riscv_make_plt_header): Cast PLT_HEADER_SIZE to
	unsigned when using with RISCV_ITYPE.
	(_bfd_riscv_relax_call): Use an unsigned foff.
 2020-08-31 20:28:10 +09:30
Cooper Qu
0861f561eb CSKY: Support attribute section. 
bfd
        * elf32-csky.c (csky_archs): Fix arch names.
        (csky_find_arch_with_name): New.
        (elf32_csky_merge_attributes): New.
        (csky_elf_merge_private_bfd_data): Add process of merge
        attribute section.
        (elf32_csky_obj_attrs_arg_type): New.
        (elf32_csky_obj_attrs_handle_unknown): New.
        (elf_backend_obj_attrs_vendor): Define.
        (elf_backend_obj_attrs_section): Define.
        (elf_backend_obj_attrs_arg_type): Define.
        (elf_backend_obj_attrs_section_type): Define.

binutils/
        * readelf.c (get_csky_section_type_name): New.
        (get_section_type_name): Add handler for CSKY.
        (display_csky_attribute): New.
        (process_arch_specific): Add handler for CSKY.
        * testsuite/binutils-all/strip-3.d: Remove .csky.attributes
        section.

elfcpp/
        * elfcpp.h (enum SHT): New enum SHT_CSKY_ATTRIBUTES.

gas/
        * gas/config/tc-csky.c (md_begin): Set attributes.
        (isa_flag): Change type to unsigned 64 bits.
        (struct csky_cpu_info): Likewise.
        (struct csky_macro_info): Likewise.
        (set_csky_attribute): New.
        * testsuite/gas/csky/802j.d: Ignore .csky.attributes section.
        * testsuite/gas/csky/all.d: Likewise.
        * testsuite/gas/csky/bsr1.d: Likewise.
        * testsuite/gas/csky/csky_vdsp.d: Likewise.
        * testsuite/gas/csky/cskyv2_all.d: Likewise.
        * testsuite/gas/csky/cskyv2_ck803r2.d: Likewise.
        * testsuite/gas/csky/cskyv2_ck860.d: Likewise.
        * testsuite/gas/csky/cskyv2_dsp.d: Likewise.
        * testsuite/gas/csky/cskyv2_elrw.d: Likewise.
        * testsuite/gas/csky/cskyv2_float.d: Likewise.
        * testsuite/gas/csky/enhance_dsp.d: Likewise.
        * testsuite/gas/csky/java.d: Likewise.
        * testsuite/gas/csky/v1_float.d: Likewise.
        * testsuite/gas/csky/v2_float_part1.d: Likewise.
        * testsuite/gas/csky/v2_float_part2.d: Likewise.
        * testsuite/gas/csky/v2_tls_gd.d: Likewise.
        * testsuite/gas/csky/v2_tls_ie.d: Likewise.
        * testsuite/gas/csky/v2_tls_ld.d: Likewise.
        * testsuite/gas/csky/v2_tls_le.d: Likewise.
        * testsuite/gas/elf/elf.exp: Add handler for CSKY.
        * testsuite/gas/elf/section2.e-csky: New.

include/
        * elf/csky.h (SHT_CSKY_ATTRIBUTES): Define.
        (Tag_CSKY_ARCH_NAME): New enum constant.
        (Tag_CSKY_CPU_NAME): Likewise.
        (Tag_CSKY_ISA_FLAGS): Likewise.
        (Tag_CSKY_DSP_VERSION): Likewise.
        (Tag_CSKY_VDSP_VERSION): Likewise.
        (Tag_CSKY_FPU_VERSION): Likewise.
        (Tag_CSKY_FPU_ABI): Likewise.
        (Tag_CSKY_FPU_ROUNDING): Likewise.
        (Tag_CSKY_FPU_DENORMAL): Likewise.
        (Tag_CSKY_FPU_Exception): Likewise.
        (Tag_CSKY_FPU_NUMBER_MODULE): Likewise.
        (Tag_CSKY_FPU_HARDFP): Likewise.
        (Tag_CSKY_MAX): Likewise.
        (VAL_CSKY_DSP_VERSION_EXTENSION): Likewise.
        (VAL_CSKY_DSP_VERSION_2): Likewise.
        (VAL_CSKY_VDSP_VERSION_1): Likewise.
        (VAL_CSKY_VDSP_VERSION_2): Likewise.
        (VAL_CSKY_FPU_ABI_SOFT): Likewise.
        (VAL_CSKY_FPU_ABI_SOFTFP): Likewise.
        (VAL_CSKY_FPU_ABI_HARD): Likewise.
        (VAL_CSKY_FPU_HARDFP_HALF): Likewise.
        (VAL_CSKY_FPU_HARDFP_SINGLE): Likewise.
        (VAL_CSKY_FPU_HARDFP_DOUBLE): Likewise.
        * opcode/csky.h (CSKY_ISA_VDSP_V2): Define.
        CSKYV1_ISA_E1: Change to long constant type.
        CSKYV2_ISA_E1: Likewise.
        CSKYV2_ISA_1E2: Likewise.
        CSKYV2_ISA_2E3: Likewise.
        CSKYV2_ISA_3E7: Likewise.
        CSKYV2_ISA_7E10: Likewise.
        CSKYV2_ISA_3E3R1: Likewise.
        CSKYV2_ISA_3E3R2: Likewise.
        CSKYV2_ISA_10E60: Likewise.
        CSKY_ISA_TRUST: Likewise.
        CSKY_ISA_CACHE: Likewise.
        CSKY_ISA_NVIC: Likewise.
        CSKY_ISA_CP: Likewise.
        CSKY_ISA_MP: Likewise.
        CSKY_ISA_MP_1E2: Likewise.
        CSKY_ISA_JAVA: Likewise.
        CSKY_ISA_MAC: Likewise.
        CSKY_ISA_MAC_DSP: Likewise.
        CSKY_ISA_DSP: Likewise.
        CSKY_ISA_DSP_1E2: Likewise.
        CSKY_ISA_DSP_ENHANCE: Likewise.
        CSKY_ISA_FLOAT_E1: Likewise.
        CSKY_ISA_FLOAT_1E2: Likewise.
        CSKY_ISA_FLOAT_1E3: Likewise.
        CSKY_ISA_FLOAT_3E4: Likewise.
        CSKY_ISA_VDSP: Likewise.

ld/
        * emulparams/cskyelf.sh: Support attribute section.
        * testsuite/ld-csky/tls-le-v1.d: Match .csky.attributes section.
        * ld/testsuite/ld-csky/tls-le.d: Likewise.
        * testsuite/ld-elf/non-contiguous.ld: Ignore .csky.attributes
        section.

opcodes/
        * csky-dis.c (CSKY_DEFAULT_ISA): Define.
        (csky_dis_info): Add member isa.
        (csky_find_inst_info): Skip instructions that do not belong to
        current CPU.
        (csky_get_disassembler): Get infomation from attribute section.
        (print_insn_csky): Set defualt ISA flag.
        * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
        * csky-opc.h (struct csky_opcode): Change isa_flag16 and
        isa_flag32'type to unsigned 64 bits.
 2020-08-28 17:23:24 +08:00
Cooper Qu
531c73a37b CSKY: Add new arch CK860. 
bfd/
        * bfd-in2.h (bfd_mach_ck860): New.
        * cpu-csky.c (arch_info_struct): Add item for CK860.

gas/
        * config/tc-csky.c (csky_archs): Add item for CK860,
        change ck810 and ck807's arch_flag.
        (csky_cpus): Add item for CK860.
        (md_begin): Enable DSP for CK810 and CK807 by default.
        (md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
        * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
        to 'sync'.
        * gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
        * gas/testsuite/gas/csky/cskyv2_ck860.d: New.
        * gas/testsuite/gas/csky/cskyv2_ck860.s: New.
        * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
        to plsli.16.
        * gas/testsuite/gas/csky/enhance_dsp.s: Likewise.

include/
        * opcode/csky.h (CSKYV2_ISA_10E60): New.
        (CSKY_ARCH_860): New.

opcode/
        * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
        in other CPUs to speed up disassembling.
        * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
        Change plsli.u16 to plsli.16, change sync's operand format.

Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc
 2020-08-24 20:27:07 +08:00
Cooper Qu
d04aee0f41 CSKY: Add ck803r2 series cpu. 
gas/
        * config/tc-csky.c (CSKY_ISA_803R2): New.
        (csky_archs): Add ck803r2 series.
        (md_begin): Fix warning about -medsp.
        (csky_get_freg_val): Support lowercase of fpu register name.
        * testsuite/gas/csky/cskyv2_ck803r2.s: New file.
        * testsuite/gas/csky/cskyv2_ck803r2.d: New file.

include/
        * csky.h (CSKYV2_ISA_3E3R2): New.

opcodes/
        * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 2020-08-24 10:25:03 +08:00
Alex Coplan
fa63795f40 aarch64: Don't assert on long sysreg names 
This patch fixes an assertion failure on long system register operands
in the AArch64 backend. See the new testcase for an input which
reproduces the issue.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing
	a long system register.
	(parse_sys_ins_reg): Likewise.
	(sysreg_hash_insert): New.
	(md_begin): Use sysreg_hash_insert() to ensure all system
	registers are no longer than the maximum length at startup.
	* testsuite/gas/aarch64/invalid-sysreg-assert.d: New test.
	* testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output.
	* testsuite/gas/aarch64/invalid-sysreg-assert.s: Input.

include/ChangeLog:

	* opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
 2020-08-10 17:44:02 +01:00
Przemyslaw Wirkus
f7cb161ea6 [aarch64] GAS doesn't validate the architecture version for any tlbi registers. Fixed with this patch. 
* gas/config/tc-aarch64.c (parse_sys_reg): Call to
	aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p.
	(parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check.
	* include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
	paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	* opcodes/aarch64-opc.c (aarch64_print_operand):
	(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
	into this function.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test.
	* gas/testsuite/gas/aarch64/sysreg-5.s: New test.
 2020-08-10 16:20:17 +01:00
Nelson Chu
08ccfccf0e RISC-V: Support debug and float CSR as the unprivileged ones. 
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec.  For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec.  User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly.  Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them.  However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.

	gas/
	* config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
	checking into riscv_csr_address.
	(riscv_csr_version_check): Likewise.
	(riscv_csr_address): New function.  Return the suitable CSR address
	after checking the ISA dependency and versions.  Issue warnings	if
	we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
	CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
	priv spec versions for them.
	(reg_csr_lookup_internal): Call riscv_csr_address to find the
	suitable CSR address.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
	priv spec warnings here.  These warnings are added by accident.
	Remove them and only focus on the ISA dependency warnings.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
	dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
	than the privileged ones.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Support the unprivileged CSR.  The versions
	of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
	* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.

	opcodes/
	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
	unprivileged CSR can also be initialized.
 2020-06-30 09:54:55 +08:00
Nelson Chu
83d7d99e75 RISC-V: Cleanup the include/opcode/riscv-opc.h. 
The include/opcode/riscv-opc.h file is no longer automatically generated,
so we remove the misleading comments and add new ones.  Besides, the CAUSE_*
macros and DECLARE_CAUSE are unused for binutils and gdb.  Therefore, remove
them, too.

	include/
	* opcode/riscv-opc.h: Cleanup and remove the unused macros.
 2020-06-30 09:38:00 +08:00
Alex Coplan
359157df20 aarch64: Normalize and sort feature bit macros 
This patch normalizes and sorts the feature bit macros in
include/opcode/aarch64.h such that it's easy to tell which bits are
allocated and where it's safe to add new feature bits.

Testing:
 * Testsuite run on aarch64-none-elf.

include/ChangeLog:

2020-06-22  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SHA2): Normalize.
	(AARCH64_FEATURE_AES): Likewise.
	(AARCH64_FEATURE_V8_4): Likewise.
	(AARCH64_FEATURE_SM4): Likewise.
	(AARCH64_FEATURE_SHA3): Likewise.
	(AARCH64_FEATURE_V8): Likewise.
	(AARCH64_FEATURE_V8_2): Likewise.
	(AARCH64_FEATURE_V8_3): Likewise.
	(AARCH64_FEATURE_FP): Likewise.
	(AARCH64_FEATURE_SIMD): Likewise.
	(AARCH64_FEATURE_CRC): Likewise.
	(AARCH64_FEATURE_LSE): Likewise.
	(AARCH64_FEATURE_PAN): Likewise.
	(AARCH64_FEATURE_LOR): Likewise.
	(AARCH64_FEATURE_RDMA): Likewise.
	(AARCH64_FEATURE_V8_1): Likewise.
	(AARCH64_FEATURE_F16): Likewise.
	(AARCH64_FEATURE_RAS): Likewise.
	(AARCH64_FEATURE_PROFILE): Likewise.
	(AARCH64_FEATURE_SVE): Likewise.
	(AARCH64_FEATURE_RCPC): Likewise.
	(AARCH64_FEATURE_COMPNUM): Likewise.
	(AARCH64_FEATURE_DOTPROD): Likewise.
	(AARCH64_FEATURE_F16_FML): Likewise.
	(AARCH64_FEATURE_V8_5): Likewise.
	(AARCH64_FEATURE_V8_6): Likewise.
	(AARCH64_FEATURE_BFLOAT16): Likewise.
	(AARCH64_FEATURE_FLAGMANIP): Likewise.
	(AARCH64_FEATURE_FRINTTS): Likewise.
	(AARCH64_FEATURE_SB): Likewise.
	(AARCH64_FEATURE_PREDRES): Likewise.
	(AARCH64_FEATURE_CVADP): Likewise.
	(AARCH64_FEATURE_RNG): Likewise.
	(AARCH64_FEATURE_BTI): Likewise.
	(AARCH64_FEATURE_SCXTNUM): Likewise.
	(AARCH64_FEATURE_ID_PFR2): Likewise.
	(AARCH64_FEATURE_SSBS): Likewise.
	(AARCH64_FEATURE_MEMTAG): Likewise.
	(AARCH64_FEATURE_TME): Likewise.
	(AARCH64_FEATURE_I8MM): Likewise.
	(AARCH64_FEATURE_F32MM): Likewise.
	(AARCH64_FEATURE_F64MM): Likewise.
	(AARCH64_FEATURE_SVE2): Likewise.
	(AARCH64_FEATURE_SVE2_AES): Likewise.
	(AARCH64_FEATURE_SVE2_BITPERM): Likewise.
	(AARCH64_FEATURE_SVE2_SM4): Likewise.
	(AARCH64_FEATURE_SVE2_SHA3): Likewise.
 2020-06-22 14:51:04 +01:00
Nelson Chu
39ff0b8123 RISC-V: Report warning when linking the objects with different priv specs. 
We do know some conflicts among different privileged specs.  For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts.  But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems.  But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs.  But the option
is still under discussion.

Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs.  This not only makes the linker more flexible,
but also warns people that the conflicts may happen.  We also need to update
the output priv spec version once the input priv spec is newer.

	bfd/
	* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
	opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
	(riscv_get_priv_spec_class): Likewise.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New function, convert
	the version numbers into string, then call riscv_get_priv_spec_class
	to get the priv spec class.
	* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
	from include/opcode/riscv.h to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New forward declaration.
	(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
	* elfnn-riscv.c (riscv_merge_attributes):  Get the priv spec classes
	of input and output objects form their priv spec attributes by
	riscv_get_priv_spec_class_from_numbers.  Report warning rather than
	errors when linking objects with differnet priv spec versions.  We do
	know v1.9.1 may have conflicts to other versions, so report the
	warning, too.  After that, update the output priv spec version to the
	newest one so far.

	gas/
	* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
	(riscv_set_default_priv_spec): Get the priv spec version from the
	priv spec attributes by riscv_get_priv_spec_class_from_numbers.

	include/
	* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
	forward declarations to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.

	opcodes/
	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
 2020-06-22 10:01:14 +08:00
Nelson Chu
d8af286fff RISC-V: Drop the privileged spec v1.9 support. 
There is a conflict between v1.9 and v1.9.1 - CSR MISA address.  MISA is
0xf10 in v1.9, but change to 0x301 in v1.9.1.  The change made MISA writable,
but may also cause risk of compatibility.  Binutils already support the
-mpriv-spec options and ELF priv attributes, which can used to choose what
privileged spec you want, and then give a correponding CSR name and address
to use.  But Gdb and other tools don't have the simialr mechanism for now.
However, there are two things can be confirmed,

1. If we don't have a way to control the priv specs, then the changes, like
MISA, will cause risk and hard to maintain.

2. We get the guarantee that the CSR address won't be reused in the future
specs, even if it is dropped.

I'm not sure if Gdb needs to care about the priv spec versions, it is still
discussing.  But drop the priv spec v1.9, and make sure that we won't reuse
the CSR address is a useful solution for now.  Also, we might drop the v1.9.1
in a year or two.  After that, specs above v1.10 should be compatible anyway.

	gas/
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.

	include/
	* opcode/riscv-opc.h: Update the defined versions of CSR from
	PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1.  Also, drop the
	MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
	* opcode/riscv.h (enum riscv_priv_spec_class): Remove
	PRIV_SPEC_CLASS_1P9.

	opcodes/
	* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 2020-06-12 09:41:20 +08:00
Alex Coplan
14962256b3 [PATCH]: aarch64: Refactor representation of system registers 
Prior to this patch, the information describing the AArch64 system
registers was separate from the information describing which system
registers are available depending on the CPU feature set. Indeed, the
latter was implemented as a separate function from the main table with
the system register information.

This patch remedies this situation and puts the feature information into
the system register table itself.

This has several advantages:

 * Having all the information described in one place is easier to
   maintain.
 * The logic to check whether a system register is supported now becomes
   trivial (and much more efficient).

Since this patch ended up touching every line of the system register
table, I took the opportunity to make the formatting more consistent and
remove some redundant comments.

Note that there is still more refactoring that could be done along the
same lines here (e.g. with the TLB instructions) but this seemed like a
reasonable first pass.

Testing:

 * Regression tested an x64 -> aarch64-none-elf cross binutils.
 * Built aarch64-none-elf cross toolchain, checked newlib startup
   code still works.
 * Bootstrapped binutils on aarch64-linux-gnu, regression tested.
 * Built aarch64 kernel using new binutils with allyesconfig.

OK for master? If so, I'll need a maintainer to commit on my behalf
since I don't have write access.

Thanks,
Alex

---

include/ChangeLog:

2020-06-11  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
	describing system registers.

opcodes/ChangeLog:

2020-06-11  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-opc.c (SYSREG): New macro for describing system registers.
	(SR_CORE): Likewise.
	(SR_FEAT): Likewise.
	(SR_RNG): Likewise.
	(SR_V8_1): Likewise.
	(SR_V8_2): Likewise.
	(SR_V8_3): Likewise.
	(SR_V8_4): Likewise.
	(SR_PAN): Likewise.
	(SR_RAS): Likewise.
	(SR_SSBS): Likewise.
	(SR_SVE): Likewise.
	(SR_ID_PFR2): Likewise.
	(SR_PROFILE): Likewise.
	(SR_MEMTAG): Likewise.
	(SR_SCXTNUM): Likewise.
	(aarch64_sys_regs): Refactor to store feature information in the table.
	(aarch64_sys_reg_supported_p): Collapse logic for system registers
	that now describe their own features.
	(aarch64_pstatefield_supported_p): Likewise.
 2020-06-11 12:34:37 +01:00
Jose E. Marchesi
e9bffec9af opcodes: discriminate endianness and insn-endianness in CGEN ports 
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value.  These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.

The process of writing an instruction to the object file is:

  a) cgen_put_insn_value        ;; Writes out the opcodes.
  b) ARCH_cgen_insert_operand
       insert_normal
         insert_1
           cgen_put_insn_value  ;; Writes out the bytes of the
                                ;; operand.

Likewise, the process of reading an instruction from the object file
is:

  a) cgen_get_insn_value        ;; Reads the opcodes.
  b) ARCH_cgen_extract_operand
       extract_normal
         extract_1
           cgen_get_insn_value  ;; Reads in the bytes of the
                                ;; operand.

As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.

This is problematic for architectures in which the endianness of
instructions is different to the endianness of data.  An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.

This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate.  Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.

A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value.  It has been adapted to
  pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
  It has been adapted to pass the new endianargument.  Ditto for a
  call in the assembler.

Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/cgen.h: Get an `endian' argument in both
	cgen_get_insn_value and cgen_put_insn_value.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen.c (gas_cgen_finish_insn): Pass the endianness to
	cgen_put_insn_value.
	(gas_cgen_md_apply_fix): Likewise.
	(gas_cgen_md_apply_fix): Likewise.
	* config/tc-bpf.c (md_apply_fix): Pass data endianness to
	cgen_put_insn_value.
	* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
	cgen_put_insn_value.

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* mep.opc (print_slot_insn): Pass the insn endianness to
	cgen_get_insn_value.
 2020-06-04 16:17:42 +02:00
Jose E. Marchesi
b3db6d07be opcodes: support insn endianness in cgen_cpu_open 
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument
for @arch@_cgen_cpu_open.  This is useful for architectures in
which the endianness of the instruction words is not the same
than the endianness used for data.

An accompanying patch has been sent to the CGEN mailing list that
adds support for this argument on the CGEN side [1].  Its been
already pre-approved [2], and will be applied simultaneously with
this binutils series.

[1] https://sourceware.org/pipermail/cgen/2020q2/002733.html
[2] https://sourceware.org/pipermail/cgen/2020q2/002737.html

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* opcode/cgen.h (enum cgen_cpu_open_arg): New value
	CGEN_CPU_OPEN_INSN_ENDIAN.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
	(print_insn_): Handle instruction endian.
	* bpf-dis.c: Regenerate.
	* bpf-desc.c: Regenerate.
	* epiphany-dis.c: Likewise.
	* epiphany-desc.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-desc.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-desc.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-desc.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-desc.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-desc.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-desc.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-desc.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-desc.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-desc.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-desc.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-desc.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-desc.c: Likewise.

binutils/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* objdump.c (disassemble_data): Set disasm_info.endian_code to
        disasm_info.endian after the latter is initialized to the
        endianness reported by BFD.
 2020-06-04 16:17:42 +02:00
Nelson Chu
44730156af RISC-V: Fix the error when building RISC-V linux native gdbserver. 
The original report is as follow,
https://sourceware.org/pipermail/binutils/2020-June/111383.html

Inlcude the bfd.h in the include/opcode/riscv.h may cause gdbserver fail
to build.  I just want to use the `bfd_boolean` in the opcodes/riscv-opc.c,
but I didn't realize this cause the build failed.  Fortunately, I can also
use the `int` as the function return types just like others in the
opcodes/riscv-opc.c.

	include/
	* opcode/riscv.h: Remove #include "bfd.h".  And change the return
	types of riscv_get_isa_spec_class and riscv_get_priv_spec_class
	from bfd_boolean to int.

	opcodes/
	* riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
	(riscv_get_priv_spec_class): Likewise.
 2020-06-03 09:20:59 +08:00
Alan Modra
8eff95bcb6 PR26044, Some targets can't be compiled with GCC 10 (tilepro) 
Since this value is used in fields of type tilepro_pipeline (as
NO_PIPELINE, see tc-tilepro.c) it is appropriate to put it in
the tilepro_pipelen enum.  This avoids a warning about converting from
one enum type to another.

	PR 26044
	* opcode/tilepro.h (TILEPRO_NUM_PIPELINE_ENCODINGS): Move to
	tilepro_pipeline enum.
 2020-05-28 21:11:51 +09:30
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
 2020-05-20 17:22:48 +01:00
Alexander Fedotov
164446e04c Fix the ARM assembler to generate a Realtime profile for armv8-r. 
PR 25992
gas	* config/tc-arm.c : Add arm_ext_v8r feature.
	(it_fsm_post_encode): Check arm_ext_v8r feature.
	(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.

include	* opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
 2020-05-19 12:45:42 +01:00
Alan Modra
aa3c112fab Power10 Reduced precision outer product operations 
include/
	* opcode/ppc.h (PPC_OPERAND_ACC): Define.  Renumber following
	PPC_OPERAND defines.
opcodes/
	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
	(md_assemble): Check acc specified in correct operand.
	* testsuite/gas/ppc/outerprod.d,
	* testsuite/gas/ppc/outerprod.s,
	* testsuite/gas/ppc/vsx4.d,
	* testsuite/gas/ppc/vsx4.s: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.
 2020-05-11 21:08:37 +09:30
Alan Modra
7c1f422735 PowerPC Rename powerxx to power10 
Now that ISA3.1 is out we can finish with the powerxx silliness.

bfd/
	* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
	* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
	renaming.
	* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
	* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
	* powerpc.cc: Rename powerxx to power10 throughout.
include/
	* elf/ppc64.h: Update comment.
	* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
	* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/ld-powerpc/notoc2.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Likewise.
	* testsuite/ld-powerpc/tlsgd.d: Likewise.
	* testsuite/ld-powerpc/tlsie.d: Likewise.
	* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
	* ppc-dis.c (ppc_opts): Add "power10" entry.
	(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
	* ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 2020-05-11 21:08:36 +09:30
Alex Coplan
09c1e68a16 AArch64: add GAS support for UDF instruction 
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
 2020-04-30 15:47:30 +01:00
Nelson Chu
d1a89da5de RISC-V: Update CSR to privileged spec 1.11. 
gas/
	* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
	* testsuite/gas/riscv/alias-csr.s: Likewise.
	* testsuite/gas/riscv/no-aliases-csr.d: Move this
	to priv-reg-pseudo-noalias.
	* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
	* testsuite/gas/riscv/bad-csr.l: Likewise.
	* testsuite/gas/riscv/bad-csr.s: Likewise.
	* testsuite/gas/riscv/satp.d: Removed.  Already included in priv-reg.
	* testsuite/gas/riscv/satp.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
	csr instruction, including alias-csr testcase.
	* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
	pseudo instruction with objdump -Mno-aliases.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
	* testsuite/gas/riscv/priv-reg.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Update CSR to 1.11.

	gdb/
	* features/riscv/32bit-csr.xml: Regenerated.
	* features/riscv/64bit-csr.xml: Regenerated.
 2020-03-30 12:24:53 -07:00
Nelson Chu
bd0cf5a6ba RISC-V: Support the ISA-dependent CSR checking. 
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set.  We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information.  We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option.  Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.

	gas/
	* config/tc-riscv.c (enum riscv_csr_class): New enum.  Used to decide
	whether or not this CSR is legal in the current ISA string.
	(struct riscv_csr_extra): New structure to hold all extra information
	of CSR.
	(riscv_init_csr_hash): New function.  According to the DECLARE_CSR and
	DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
	Call hash_reg_name to insert CSR address into reg_names_hash.
	(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
	(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
	Decide whether the CSR is valid according to the csr_extra_hash.
	(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
	not a boolean.  This is same as riscv_init_csr_hash, so keep the
	consistent usage.

	* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
	* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase.  The source
	file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
	f-ext CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase.  The
	source file is `priv-reg.s`, and the ISA is rv64if, so the
	rv32-only CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.

	include/
	* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
	record riscv_csr_class.

	opcodes/
	* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.

	gdb/
	* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
	* riscv-tdep.h: Likewise.
	* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
	rv32-only CSR.
	* features/riscv/64bit-csr.xml: Regernated.

	binutils/
	* dwarf.c: Updated since the DECLARE_CSR is changed.
 2020-02-20 16:49:09 -08:00
Matthew Malcomson
4934a27c8c [binutils][arm] arm support for ARMv8.m Custom Datapath Extension 
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.

This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.

The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags.  This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.

We introduce a new IT block state to indicate the behaviour of these
instructions.  This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them.  Hence
we need to mark an instruction as allowed in either position.

We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_ext_cde*): New feature sets for each
	CDE coprocessor that can be enabled.
	(enum pred_instruction_type): New pred type.
	(BAD_NO_VPT): New error message.
	(BAD_CDE): New error message.
	(BAD_CDE_COPROC): New error message.
	(enum operand_parse_code): Add new immediate operands.
	(parse_operands): Account for new immediate operands.
	(check_cde_operand): New.
	(cde_coproc_enabled): New.
	(cde_coproc_pos): New.
	(cde_handle_coproc): New.
	(cxn_handle_predication): New.
	(do_custom_instruction_1): New.
	(do_custom_instruction_2): New.
	(do_custom_instruction_3): New.
	(do_cx1): New.
	(do_cx1a): New.
	(do_cx1d): New.
	(do_cx1da): New.
	(do_cx2): New.
	(do_cx2a): New.
	(do_cx2d): New.
	(do_cx2da): New.
	(do_cx3): New.
	(do_cx3a): New.
	(do_cx3d): New.
	(do_cx3da): New.
	(handle_pred_state): Define new IT block behaviour.
	(insns): Add newn CX*{,d}{,a} instructions.
	(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
	Define new cdecp extension strings.
	* doc/c-arm.texi: Document new cdecp extension arguments.
	* testsuite/gas/arm/cde-scalar.d: New test.
	* testsuite/gas/arm/cde-scalar.s: New test.
	* testsuite/gas/arm/cde-warnings.d: New test.
	* testsuite/gas/arm/cde-warnings.l: New test.
	* testsuite/gas/arm/cde-warnings.s: New test.
	* testsuite/gas/arm/cde.d: New test.
	* testsuite/gas/arm/cde.s: New test.

include/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
	(ARM_EXT2_CDE0): New extension macro.
	(ARM_EXT2_CDE1): New extension macro.
	(ARM_EXT2_CDE2): New extension macro.
	(ARM_EXT2_CDE3): New extension macro.
	(ARM_EXT2_CDE4): New extension macro.
	(ARM_EXT2_CDE5): New extension macro.
	(ARM_EXT2_CDE6): New extension macro.
	(ARM_EXT2_CDE7): New extension macro.

opcodes/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.
 2020-02-10 16:50:14 +00:00
Alan Modra
c5d7be0c97 ubsan: d30v: negation of -2147483648 
include/
	* opcode/d30v.h (struct pd_reg): Make value field unsigned.
opcodes/
	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 2020-02-04 14:10:40 +10:30
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature 
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
 2020-01-16 14:33:01 +00:00
Jozef Lawrynowicz
131cb553d6 MSP430: Fix relocation overflow when using #lo(EXP) macro 
gas/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
	relocations when the target is 430X, except when extracting part of an
	expression.
	(msp430_srcoperand): Adjust comment.
	Initialize the expp member of the msp430_operand_s struct as
	appropriate.
	(msp430_dstoperand): Likewise.
	* testsuite/gas/msp430/msp430.exp: Run new test.
	* testsuite/gas/msp430/reloc-lo-430x.d: New test.
	* testsuite/gas/msp430/reloc-lo-430x.s: New test.

include/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* opcode/msp430.h (enum msp430_expp_e): New.
	(struct msp430_operand_s): Add expp member to struct.

ld/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* testsuite/ld-msp430-elf/msp430-elf.exp: Run new test.
	* testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
 2020-01-15 13:23:06 +00:00
Alan Modra
5496abe1c5 tic4x: sign extension using shifts 
Don't do that.  Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long.  Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.

include/
	* opcode/tic4x.h (EXTR): Delete.
	(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
	extension using shifts.  Do trim INSERTU value to specified bitfield.
opcodes/
	* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
	* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
	insertion.
 2020-01-13 12:12:05 +10:30