36 lines
3.2 KiB
HTML
36 lines
3.2 KiB
HTML
<html>
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<head>
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<title>MatCat's 8SA1 CPU ISA Documentation</title>
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</head>
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<body style="font-family: monospace; font-size: 1.5em;">
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<div style="font-size: 0.9em;">
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<h3>Architecture</h3>
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<p>The 8SA1 is an 8 bit computer, with a 16 bit data bus, 16 bit program counter and stack pointer, and 24 bit address control. Since the data bus is 16 bits wide memory is also 16 bits wide. The computer uses a a simple microcode architecture that allows for up to 16 microcode steps per instruction. Further microcode instructions can be reset not just to 0 for a new instruction, but also to 8 to allow for loops inside of an instruction. The decoder uses the 4 bits of the microcode step counter, then the 10 least significant bits of the instruction optcode, followed by the zero/negative and carry/overflow flags for a 16 bit microcode lookup. This configuration allows for a total of 1024 possible instructions irregardless of conditional use. </p>
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<h3>Registers</h3>
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<p>The 8SA1 has 4 general purpose 8 bit registers, labeled A, B, C and D. These registers can be read and written selectively to either the high or low byte of the data bus, and can be combined together to get 16 bit word values for use in 16 bit registers, or from 16 bit registers to any 2 general purpose registers. The Program Counter (PC) and Stack Pointer (SP)</p>
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<p>The CPU also has some special registers, which will be described below.</p>
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<ul>
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<li>[16b] PC - Program Counter, <span>Holds the address of the next instruction or instruction operand data. Defaults to starting at 0x0000</span></li>
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<li>[ 8b] HRP - HIGH RAM Page, <span>Holds the 8 most significant bits of the 24 bit RAM address, changing this immediately changes the ram address. This can not be directly set via an instruction but can be read.</span></li>
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<li>[16b] SP - Stack Pointer, <span>This is a pointer to the current location in RAM where the next stack entry is located. Defaults to starting at 0xFFFF</span></li>
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<li>[ 8b] SPP - Stack Pointer Page, <span>The value of this register will determine the 8 most significant bytes of the full 24 bit address for the stack. Defaults to starting at 0xCF</span></li>
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<li>[ 8b] SR - Status Register, <span>Contains special status flags for the CPU.</span></li>
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<li>[16b] IR - Instruction Register, <span>This register is not accessible via code, this is where an instruction once loaded by the CPU goes until the next instruction is loaded.</span></li>
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<li>[16b] IR2 - Instruction Register 2, <span>This register is not accessible via code, it is used by the CPU when reading instruction with 2 operand words.</span></li>
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<li>[16b] CO - Control Line Register, <span>This register is not accessible via code, it is part of the fetch/decode cycle to retrieve the control line definition for the given microcode step of an instruction.</span></li>
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</ul>
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<p></p>
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</div>
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<div id="isa_list">
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</div>
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<script src="js/defines.js"></script>
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<script src="js/microcode_compiler.js"></script>
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<script src="js/asm_compiler.js"></script>
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<script src="js/instruction_doc.js"></script>
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</body>
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</html>
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