MatCat.OpenSource/8SA1Sim
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

More instructions, more docs, more yay

Browse Source
This commit is contained in:
MatCat 2021-04-10 01:08:33 -07:00
parent 6168e57ab1
commit 14ebbbd9e8
6 changed files with 598 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
README.md
View File

@ -1,3 +1,54 @@
# MatCat 8SA1 CPU Simulator
This is a simple JS based simulator to simulate the function of the 8SA1 CPU.
This is a simple JS based simulator to simulate the function of the 8SA1 CPU.
## Work In Progress
### ISA Layout
#### LDx 0x0000:0x00FF / STx 0x0100:0x01FF
| bits | mode |
| --- | --- |
| 0b000XXXXX | Immediate (8/16) |
| 0b001XXXXX | Absolute + (Immediate (16) Offset) |
| 0b010XXXXX | Absolute (16) |
| 0b011XXXXX | Absolute (24) |
| 0b100XXXXX | Indirect (16) |
| 0b101XXXXX | Indirect (24) |
| 0b110XXXXX | Indirect + (Immediate (16) Offset) |
| 0b111XXXXX | Absolute + (Absolute (16) Offset) |
| Registers | bits |
| --- | --- |
| AL | 0b00010 0x02 |
| AH | 0b00011 0x03 |
| BL | 0b00100 0x04 |
| BH | 0b00101 0x05 |
| CL | 0b00110 0x06 |
| CH | 0b00111 0x07 |
| DL | 0b01000 0x08 |
| DH | 0b01001 0x09 |
| AB | 0b01010 0x0A |
| AC | 0b01011 0x0B |
| AD | 0b01100 0x0C |
| BA | 0b01101 0x0D |
| BC | 0b01110 0x0E |
| BD | 0b01111 0x0F |
| CA | 0b10000 0x10 |
| CB | 0b10001 0x11 |
| CD | 0b10010 0x12 |
| DA | 0b10011 0x13 |
| DB | 0b10100 0x14 |
| DC | 0b10101 0x15 |
#### Tx 0x0200:0x027F
#### PHx/PLx 0x0280:0x02BF
#### Jumps 0x2C0 - 0x2FF
#### ALU 0x0300 - 0x3DF
#### NOP 0x3FF

20
isa.html
View File

@ -4,6 +4,26 @@
</head>
<body style="font-family: monospace; font-size: 1.5em;">
<div style="font-size: 0.9em;">
<h3>Architecture</h3>
<p>The 8SA1 is an 8 bit computer, with a 16 bit data bus, 16 bit program counter and stack pointer, and 24 bit address control. Since the data bus is 16 bits wide memory is also 16 bits wide. The computer uses a a simple microcode architecture that allows for up to 16 microcode steps per instruction. Further microcode instructions can be reset not just to 0 for a new instruction, but also to 8 to allow for loops inside of an instruction. The decoder uses the 4 bits of the microcode step counter, then the 10 least significant bits of the instruction optcode, followed by the zero/negative and carry/overflow flags for a 16 bit microcode lookup. This configuration allows for a total of 1024 possible instructions irregardless of conditional use. </p>
<h3>Registers</h3>
<p>The 8SA1 has 4 general purpose 8 bit registers, labeled A, B, C and D. These registers can be read and written selectively to either the high or low byte of the data bus, and can be combined together to get 16 bit word values for use in 16 bit registers, or from 16 bit registers to any 2 general purpose registers. The Program Counter (PC) and Stack Pointer (SP)</p>
<p>The CPU also has some special registers, which will be described below.</p>
<ul>
<li>[16b] PC&nbsp;&nbsp;- Program Counter, <span>Holds the address of the next instruction or instruction operand data. Defaults to starting at 0x0000</span></li>
<li>[ 8b] HRP - HIGH RAM Page, <span>Holds the 8 most significant bits of the 24 bit RAM address, changing this immediately changes the ram address. This can not be directly set via an instruction but can be read.</span></li>
<li>[16b] SP&nbsp;&nbsp;- Stack Pointer, <span>This is a pointer to the current location in RAM where the next stack entry is located. Defaults to starting at 0xFFFF</span></li>
<li>[ 8b] SPP - Stack Pointer Page, <span>The value of this register will determine the 8 most significant bytes of the full 24 bit address for the stack. Defaults to starting at 0xCF</span></li>
<li>[ 8b] SR&nbsp;&nbsp;- Status Register, <span>Contains special status flags for the CPU.</span></li>
<li>[16b] IR&nbsp;&nbsp;- Instruction Register, <span>This register is not accessible via code, this is where an instruction once loaded by the CPU goes until the next instruction is loaded.</span></li>
<li>[16b] IR2 - Instruction Register 2, <span>This register is not accessible via code, it is used by the CPU when reading instruction with 2 operand words.</span></li>
<li>[16b] CO&nbsp;&nbsp;- Control Line Register, <span>This register is not accessible via code, it is part of the fetch/decode cycle to retrieve the control line definition for the given microcode step of an instruction.</span></li>
</ul>
<p></p>
</div>
<div id="isa_list">
</div>

3
js/defines.js
View File

@ -62,10 +62,13 @@ const OECONTROL_CD = 0b10010 // GPD to HIGH, GPC to LOW
const OECONTROL_DA = 0b10011 // GPA to HIGH, GPD to LOW
const OECONTROL_DB = 0b10100 // GPB to HIGH, GPD to LOW
const OECONTROL_DC = 0b10101 // GPC to HIGH, GPD to LOW
// 10110
// 10111
const OECONTROL_I2 = 0b11000 // RAM Out, IR2 In
const OECONTROL_2O = 0b11001 // IR2 Out
const OECONTROL_HO = 0b11010 // HIGH Ram to DATABUS LOW
const OECONTROL_HS = 0b11011 // Stack Page Byte out to ADDRBUS HIGH (disables RH out)
const OECONTROL_SS = 0b11100 // GPA to LOW, Status Register IN
const OECONTROL_AO = 0b11101 // ALU Output to LOW
const OECONTROL_SR = 0b11110 // Status Register to LOW
const OECONTROL_RO = 0b11111 // RAM to DATABUS Enable

1
js/instruction_doc.js
View File

@ -21,6 +21,7 @@ for (let a = 0; a < Instructions.length; a++) {
}
let outHTML = "";
ISAPrepList.sort((a, b) => (a.Bytecode > b.Bytecode) ? -1 : 1);
for (let a = 0; a < ISAPrepList.length; a++) {
outHTML += `<div style="width: 60%; background-color: #eee;">`;
outHTML += `<h4>${ISAPrepList[a].Mnemonic}&nbsp;&nbsp;&nbsp;&nbsp;${ISAPrepList[a].LongName} </h4>`;

3
js/main.js
View File

@ -1,5 +1,6 @@
let cpu = new CPU_8SA1();
GenerateMicrocode(Instructions,cpu);
cpu.RAM[0] = is_LDSPP_i.Bytecode;
cpu.RAM[1] = 0xCF;
cpu.RAM[2] = is_LDAB_i.Bytecode;
@ -8,8 +9,6 @@ cpu.RAM[4] = is_PHAB.Bytecode;
cpu.RAM[5] = is_PJSR.Bytecode;
cpu.RAM[6] = 0x00D0;
cpu.RAM[0x80000] = is_RTS.Bytecode;
let v_printloop = 0xd9;
let v_rollover = 0xe8;
let v_return = 0xf0;

575
js/microcode_compiler.js
View File

@ -32,6 +32,16 @@ const CONTROL_MCL0 = 0b01000000000000000000000000000000; // Micro
const CONTROL_MCL8 = 0b10000000000000000000000000000000; // Microcode Counter to 8
*/
/*
Free Instructions:
0x000
0x001
0x003
0x005
0x007
0x009
*/
let Instructions = new Array();
const InstructionTypes = {
@ -191,10 +201,10 @@ class Microcode_Instruction {
//--------------------------- General Purpose Registers LDx Immediates ---------------------------
class IS_LDA_imm extends Microcode_Instruction {
class IS_LDA_imm8 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x000;
this.Bytecode = 0x002;
this.Mnemonic = "LDA";
this.LongName = "LOAD Register A";
this.Aliases = new Array();
@ -209,13 +219,13 @@ class IS_LDA_imm extends Microcode_Instruction {
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_PCC;
}
}
is_LDA_i = new IS_LDA_imm;
is_LDA_i = new IS_LDA_imm8;
Instructions.push(is_LDA_i);
class IS_LDB_imm extends Microcode_Instruction {
class IS_LDB_imm8 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x001;
this.Bytecode = 0x004;
this.Mnemonic = "LDB";
this.LongName = "LOAD Register B";
this.Aliases = new Array();
@ -228,13 +238,13 @@ class IS_LDB_imm extends Microcode_Instruction {
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_PCC;
}
}
is_LDB_i = new IS_LDB_imm;
is_LDB_i = new IS_LDB_imm8;
Instructions.push(is_LDB_i);
class IS_LDC_imm extends Microcode_Instruction {
class IS_LDC_imm8 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x002;
this.Bytecode = 0x006;
this.Mnemonic = "LDC";
this.LongName = "LOAD Register C";
this.Aliases = new Array();
@ -247,13 +257,13 @@ class IS_LDC_imm extends Microcode_Instruction {
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_PCC;
}
}
is_LDC_i = new IS_LDC_imm;
is_LDC_i = new IS_LDC_imm8;
Instructions.push(is_LDC_i);
class IS_LDD_imm extends Microcode_Instruction {
class IS_LDD_imm8 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x003;
this.Bytecode = 0x008;
this.Mnemonic = "LDD";
this.LongName = "LOAD Register D";
this.Aliases = new Array();
@ -266,16 +276,246 @@ class IS_LDD_imm extends Microcode_Instruction {
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_PCC;
}
}
is_LDD_i = new IS_LDD_imm;
is_LDD_i = new IS_LDD_imm8;
Instructions.push(is_LDD_i);
class IS_LDAB_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00A;
this.Mnemonic = "LDAB";
this.LongName = "LOAD Register A and B";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_RBIH | CONTROL_PCC;
}
}
is_LDAB_i = new IS_LDAB_imm16;
Instructions.push(is_LDAB_i);
class IS_LDAC_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00B;
this.Mnemonic = "LDAC";
this.LongName = "LOAD Register A and C";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_RCIH | CONTROL_PCC;
}
}
is_LDAC_i = new IS_LDAC_imm16;
Instructions.push(is_LDAC_i);
class IS_LDAD_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00C;
this.Mnemonic = "LDAD";
this.LongName = "LOAD Register A and D";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_RDIH | CONTROL_PCC;
}
}
is_LDAD_i = new IS_LDAD_imm16;
Instructions.push(is_LDAD_i);
class IS_LDBA_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00D;
this.Mnemonic = "LDBA";
this.LongName = "LOAD Register B and A";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_RAIH | CONTROL_PCC;
}
}
is_LDBA_i = new IS_LDBA_imm16;
Instructions.push(is_LDBA_i);
class IS_LDBC_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00E;
this.Mnemonic = "LDBC";
this.LongName = "LOAD Register B and C";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_RCIH | CONTROL_PCC;
}
}
is_LDBC_i = new IS_LDBC_imm16;
Instructions.push(is_LDBC_i);
class IS_LDBD_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00F;
this.Mnemonic = "LDBD";
this.LongName = "LOAD Register B and D";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_RDIH | CONTROL_PCC;
}
}
is_LDBD_i = new IS_LDBD_imm16;
Instructions.push(is_LDBD_i);
class IS_LDCA_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x010;
this.Mnemonic = "LDCA";
this.LongName = "LOAD Register C and A";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_RAIH | CONTROL_PCC;
}
}
is_LDCA_i = new IS_LDCA_imm16;
Instructions.push(is_LDCA_i);
class IS_LDCB_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x011;
this.Mnemonic = "LDCB";
this.LongName = "LOAD Register C and B";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_RBIH | CONTROL_PCC;
}
}
is_LDCB_i = new IS_LDCB_imm16;
Instructions.push(is_LDCB_i);
class IS_LDCD_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x012;
this.Mnemonic = "LDCD";
this.LongName = "LOAD Register C and D";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_RDIH | CONTROL_PCC;
}
}
is_LDCD_i = new IS_LDCD_imm16;
Instructions.push(is_LDCD_i);
class IS_LDDA_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x013;
this.Mnemonic = "LDDA";
this.LongName = "LOAD Register D and A";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_RAIH | CONTROL_PCC;
}
}
is_LDDA_i = new IS_LDDA_imm16;
Instructions.push(is_LDDA_i);
class IS_LDDB_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x014;
this.Mnemonic = "LDDB";
this.LongName = "LOAD Register D and B";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_RBIH | CONTROL_PCC;
}
}
is_LDDB_i = new IS_LDDB_imm16;
Instructions.push(is_LDDB_i);
class IS_LDDC_imm16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x015;
this.Mnemonic = "LDDC";
this.LongName = "LOAD Register D and C";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_RCIH | CONTROL_PCC;
}
}
is_LDDC_i = new IS_LDDC_imm16;
Instructions.push(is_LDDC_i);
//--------------------------- General Purpose Registers LDx Absolutes ---------------------------
class IS_LDA_abs extends Microcode_Instruction {
class IS_LDA_abs16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x004;
this.Bytecode = 0x042;
this.Mnemonic = "LDA";
this.LongName = "LOAD Register A";
this.Aliases = new Array();
@ -290,13 +530,13 @@ class IS_LDA_abs extends Microcode_Instruction {
this.Microcode[4] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_PCC;
}
}
is_LDA_a = new IS_LDA_abs;
is_LDA_a = new IS_LDA_abs16;
Instructions.push(is_LDA_a);
class IS_LDB_abs extends Microcode_Instruction {
class IS_LDB_abs16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x005;
this.Bytecode = 0x044;
this.Mnemonic = "LDB";
this.LongName = "LOAD Register B";
this.Aliases = new Array();
@ -310,13 +550,13 @@ class IS_LDB_abs extends Microcode_Instruction {
this.Microcode[4] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_PCC;
}
}
is_LDB_a = new IS_LDB_abs;
is_LDB_a = new IS_LDB_abs16;
Instructions.push(is_LDB_a);
class IS_LDC_abs extends Microcode_Instruction {
class IS_LDC_abs16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x006;
this.Bytecode = 0x046;
this.Mnemonic = "LDC";
this.LongName = "LOAD Register C";
this.Aliases = new Array();
@ -330,13 +570,13 @@ class IS_LDC_abs extends Microcode_Instruction {
this.Microcode[4] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_PCC;
}
}
is_LDC_a = new IS_LDC_abs;
is_LDC_a = new IS_LDC_abs16;
Instructions.push(is_LDC_a);
class IS_LDD_abs extends Microcode_Instruction {
class IS_LDD_abs16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x007;
this.Bytecode = 0x048;
this.Mnemonic = "LDD";
this.LongName = "LOAD Register D";
this.Aliases = new Array();
@ -350,15 +590,128 @@ class IS_LDD_abs extends Microcode_Instruction {
this.Microcode[4] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_PCC;
}
}
is_LDD_a = new IS_LDD_abs;
is_LDD_a = new IS_LDD_abs16;
Instructions.push(is_LDD_a);
class IS_LDA_abs24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x062;
this.Mnemonic = "LDA";
this.LongName = "LOAD Register A";
this.Aliases = new Array();
this.Type = InstructionTypes.Absolute;
this.Operands = new Array({Operand: "", Bitwidth: 24});
this.Words = 3;
this.Cycles = 12;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_PCC;
this.Microcode[10] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[11] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDA_a24 = new IS_LDA_abs24;
Instructions.push(is_LDA_a24);
class IS_LDB_abs24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x064;
this.Mnemonic = "LDB";
this.LongName = "LOAD Register B";
this.Aliases = new Array();
this.Type = InstructionTypes.Absolute;
this.Operands = new Array({Operand: "", Bitwidth: 24});
this.Words = 3;
this.Cycles = 12;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_PCC;
this.Microcode[10] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[11] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDB_a24 = new IS_LDB_abs24;
Instructions.push(is_LDB_a24);
class IS_LDC_abs24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x066;
this.Mnemonic = "LDC";
this.LongName = "LOAD Register C";
this.Aliases = new Array();
this.Type = InstructionTypes.Absolute;
this.Operands = new Array({Operand: "", Bitwidth: 24});
this.Words = 3;
this.Cycles = 12;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_PCC;
this.Microcode[10] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[11] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDC_a24 = new IS_LDC_abs24;
Instructions.push(is_LDC_a24);
class IS_LDD_abs24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x068;
this.Mnemonic = "LDD";
this.LongName = "LOAD Register D";
this.Aliases = new Array();
this.Type = InstructionTypes.Absolute;
this.Operands = new Array({Operand: "", Bitwidth: 24});
this.Words = 3;
this.Cycles = 12;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_PCC;
this.Microcode[10] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[11] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDD_a24 = new IS_LDD_abs24;
Instructions.push(is_LDD_a24);
//--------------------------- General Purpose Registers LDx Indirect ---------------------------
class IS_LDA_ind extends Microcode_Instruction {
class IS_LDA_ind16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x008;
this.Bytecode = 0x082;
this.Mnemonic = "LDA";
this.LongName = "LOAD Register A";
this.Aliases = new Array();
@ -374,13 +727,13 @@ class IS_LDA_ind extends Microcode_Instruction {
this.Microcode[5] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_PCC;
}
}
is_LDA_in = new IS_LDA_ind;
is_LDA_in = new IS_LDA_ind16;
Instructions.push(is_LDA_in);
class IS_LDB_ind extends Microcode_Instruction {
class IS_LDB_ind16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x009;
this.Bytecode = 0x084;
this.Mnemonic = "LDB";
this.LongName = "LOAD Register B";
this.Aliases = new Array();
@ -395,13 +748,13 @@ class IS_LDB_ind extends Microcode_Instruction {
this.Microcode[5] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_PCC;
}
}
is_LDB_in = new IS_LDB_ind;
is_LDB_in = new IS_LDB_ind16;
Instructions.push(is_LDB_in);
class IS_LDC_ind extends Microcode_Instruction {
class IS_LDC_ind16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00A;
this.Bytecode = 0x086;
this.Mnemonic = "LDC";
this.LongName = "LOAD Register C";
this.Aliases = new Array();
@ -416,13 +769,13 @@ class IS_LDC_ind extends Microcode_Instruction {
this.Microcode[5] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_PCC;
}
}
is_LDC_in = new IS_LDC_ind;
is_LDC_in = new IS_LDC_ind16;
Instructions.push(is_LDC_in);
class IS_LDD_ind extends Microcode_Instruction {
class IS_LDD_ind16 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x00B;
this.Bytecode = 0x088;
this.Mnemonic = "LDD";
this.LongName = "LOAD Register D";
this.Aliases = new Array();
@ -437,9 +790,124 @@ class IS_LDD_ind extends Microcode_Instruction {
this.Microcode[5] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_PCC;
}
}
is_LDD_in = new IS_LDD_ind;
is_LDD_in = new IS_LDD_ind16;
Instructions.push(is_LDD_in);
class IS_LDA_ind24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x0C2;
this.Mnemonic = "LDA";
this.LongName = "LOAD Register A";
this.Aliases = new Array();
this.Type = InstructionTypes.Indirect;
this.Operands = new Array({Operand: "#", Bitwidth: 24});
this.Words = 3;
this.Cycles = 13;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[10] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_PCC;
this.Microcode[11] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[12] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDA_in24 = new IS_LDA_ind24;
Instructions.push(is_LDA_in24);
class IS_LDB_ind24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x0C4;
this.Mnemonic = "LDB";
this.LongName = "LOAD Register B";
this.Aliases = new Array();
this.Type = InstructionTypes.Indirect;
this.Operands = new Array({Operand: "#", Bitwidth: 24});
this.Words = 3;
this.Cycles = 13;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[10] = CONTROL_OUT_RO | CONTROL_RBIL | CONTROL_PCC;
this.Microcode[11] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[12] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDB_in24 = new IS_LDB_ind24;
Instructions.push(is_LDB_in24);
class IS_LDC_ind24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x0C6;
this.Mnemonic = "LDC";
this.LongName = "LOAD Register C";
this.Aliases = new Array();
this.Type = InstructionTypes.Indirect;
this.Operands = new Array({Operand: "#", Bitwidth: 24});
this.Words = 3;
this.Cycles = 13;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[10] = CONTROL_OUT_RO | CONTROL_RCIL | CONTROL_PCC;
this.Microcode[11] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[12] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDC_in24 = new IS_LDC_ind24;
Instructions.push(is_LDC_in24);
class IS_LDD_ind24 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x0C8;
this.Mnemonic = "LDD";
this.LongName = "LOAD Register D";
this.Aliases = new Array();
this.Type = InstructionTypes.Indirect;
this.Operands = new Array({Operand: "#", Bitwidth: 24});
this.Words = 3;
this.Cycles = 13;
this.Microcode[2] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_HO | CONTROL_RI;
this.Microcode[4] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[5] = CONTROL_OUT_I2 | CONTROL_PCC;
this.Microcode[6] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[7] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[8] = CONTROL_OUT_2O | CONTROL_RHI;
this.Microcode[9] = CONTROL_OUT_RO | CONTROL_RRI;
this.Microcode[10] = CONTROL_OUT_RO | CONTROL_RDIL | CONTROL_PCC;
this.Microcode[11] = CONTROL_OUT_SP | CONTROL_RRI;
this.Microcode[12] = CONTROL_OUT_RO | CONTROL_RHI;
}
}
is_LDD_in24 = new IS_LDD_ind24;
Instructions.push(is_LDD_in24);
class IS_LDAB_GPCD extends Microcode_Instruction {
constructor(props) {
@ -460,24 +928,6 @@ class IS_LDAB_GPCD extends Microcode_Instruction {
is_LDAB_GPCD = new IS_LDAB_GPCD;
Instructions.push(is_LDAB_GPCD);
class IS_LDAB_imm extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x021;
this.Mnemonic = "LDAB";
this.LongName = "LOAD Register A and B";
this.Aliases = new Array();
this.Type = InstructionTypes.Immediate;
this.Operands = new Array({Operand: "$", Bitwidth: 16});
this.Words = 2;
this.Cycles = 4;
this.Microcode[2] = CONTROL_OUT_PC | CONTROL_RRI;
this.Microcode[3] = CONTROL_OUT_RO | CONTROL_RAIL | CONTROL_RBIH | CONTROL_PCC;
}
}
is_LDAB_i = new IS_LDAB_imm;
Instructions.push(is_LDAB_i);
class IS_LDAB_abs extends Microcode_Instruction {
constructor(props) {
@ -1878,3 +2328,20 @@ class IS_NOP extends Microcode_Instruction {
is_NOP = new IS_NOP;
Instructions.push(is_NOP);
class IS_NOP0 extends Microcode_Instruction {
constructor(props) {
super(props);
this.Bytecode = 0x0;
this.Mnemonic = "NOP";
this.LongName = "NO OPERATION";
this.Aliases = new Array();
this.Type = InstructionTypes.SingleWord;
this.Operands = new Array();
this.Words = 1;
this.Cycles = 2;
}
}
is_NOP0 = new IS_NOP0;
Instructions.push(is_NOP0);