* sparc/sparc.h (MASK_LIVE_G0,TARGET_LIVE_G0): Define.
(TARGET_SWITCHES): Add live-g0.
(FIRST_PSEUDO_REGISTER): Add 1 for %icc (now 101).
(FIXED_REGISTERS,CALL_USED_REGISTERS): Update.
(FIXED_REGISTERS): %g0 is fixed by default.
(SPARC_{FIRST,LAST}_V9_FCC_REG): Define.
(SPARC_{ICC,FCC}_REG): Define.
(CONDITIONAL_REGISTER_USAGE): Don't fix %fcc0 if v8.
(REG_CLASS_CONTENTS): Reg 0 is an int reg, reg 100 is %icc.
(REGNO_REG_CLASS): Rewrite to use global `sparc_regno_reg_class'.
(REG_ALLOC_ORDER,REG_LEAF_ALLOC_ORDER,LEAF_REGISTERS): Add %icc.
(REG_CLASS_FROM_LETTER): Handle 'c' for FPCC_REGS in non-v9 case.
(REGNO_OK_FOR_{BASE,INDEX}_P): Treat %g0 as a normal reg.
(REG_OK_FOR_{BASE,INDEX}_P,EXTRA_CONSTRAINT): Likewise.
(REGISTER_NAMES): Add %icc.
(ADDITIONAL_REGISTER_NAMES): Use SPARC_ICC_REG.
* sparc/sparc.c (leaf_reg_remap): Add %icc=100.
(reg_or_0_operand): Don't allow 0 if TARGET_LIVE_G0.
(fcc_reg_operand): Renamed from ccfp_reg_operand.
Use SPARC_FCC_REG. Don't treat reg 0 as an fcc reg. Don't match
modes if `mode' argument is VOIDmode.
(icc_or_fcc_reg_operand): New function.
(gen_compare_reg): Use SPARC_FCC_REG for v8 fp compares.
Use SPARC_ICC_REG for int compares.
(eligible_for_epilogue_delay): Don't allow anything if TARGET_LIVE_G0.
Delete unnecessary test for %g0.
(emit_move_sequence): Don't emit (set (mem) (const_int 0)) if
TARGET_LIVE_G0.
(output_scc_insn): Label moved to operand 3. Condition code reg
moved to operand 2.
(sparc_mode_class): Enum C_MODE renamed to CC_MODE.
(hard_32bit_mode_classes): Set reg 0 to S_MODES. Add entry for %icc.
(hard_64bit_mode_classes): Set reg 0 to D_MODES. Add entry for %icc.
(sparc_regno_reg_class): New global.
(sparc_init_modes): Initialize it.
(output_cbranch): Delete fp_cond_reg argument.
(print_operand, MEM op): Don't print "%g0+" if TARGET_SPARCLET.
(sparc_flat_eligible_for_epilogue_delay): Don't allow anything if
TARGET_LIVE_G0.
* sparc/sparc.md (live_g0): New attribute.
(*): Integer condition code register is now reg 100.
Use SPARC_ICC_REG instead of hardcoding reg 100 where possible.
Non-v9 floating point condition code register is now reg 96.
(*cmp{sf,df,tf}_{fpe,fp}_sp{32,64}): Combine v9/non-v9 cases.
(*{normal,inverted}_{,fp,fpe}_branch): Update call to output_cbranch.
(*mov{qi,hi,si}_insn): Don't use if TARGET_LIVE_G0.
(*mov{qi,hi,si}_insn_liveg0): New patterns.
(*mov{si,di,sf,df,tf}_ccfp{,e}_sp64): ccfp_reg_operand renamed to
fcc_reg_operand.
(*negdi2_sp32,negsi2,one_cmplsi2,ffssi2): Ensure %%g0 is 0 if
TARGET_LIVE_G0.
(*one_cmpldi2_sp32): Move operand 1 to rs1 and use 0 as rs2.
(patterns that use %g0 in rs2): Use 0 immediate value instead.
(patterns that read %g0): Don't use if TARGET_LIVE_G0.
From-SVN: r11494
c4ce68534a