89 lines
2.6 KiB
Plaintext
89 lines
2.6 KiB
Plaintext
Analysis of cycle costs for SH4:
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-> udiv_le128: 5
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-> udiv_ge64k: 6
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-> udiv udiv_25: 10
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-> pos_divisor: 3
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-> pos_result linear: 5
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-> pos_result - -: 5
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-> div_le128: 7
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-> div_ge64k: 9
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sdivsi3 -> udiv_25 13
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udiv25 -> div_ge64k_end: 15
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div_ge64k_end -> rts: 13
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div_le128 -> div_le128_2: 2, r1 latency 3
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udiv_le128 -> div_le128_2: 2, r1 latency 3
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(u)div_le128 -> div_by_1: 9
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(u)div_le128 -> rts: 17
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div_by_1(_neg) -> rts: 4
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div_ge64k -> div_r8: 2
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div_ge64k -> div_ge64k_2: 3
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udiv_ge64k -> udiv_r8: 3
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udiv_ge64k -> div_ge64k_2: 3 + LS
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(u)div_ge64k -> div_ge64k_end: 13
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div_r8 -> div_r8_2: 2
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udiv_r8 -> div_r8_2: 2 + LS
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(u)div_r8 -> rts: 21
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-> - + neg_result: 5
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-> + - neg_result: 5
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-> div_le128_neg: 7
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-> div_ge64k_neg: 9
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-> div_r8_neg: 11
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-> <64k div_ge64k_neg_end: 28
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-> >=64k div_ge64k_neg_end: 22
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div_ge64k_neg_end ft -> rts: 14
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div_r8_neg_end -> rts: 4
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div_r8_neg -> div_r8_neg_end: 18
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div_le128_neg -> div_by_1_neg: 4
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div_le128_neg -> rts 18
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sh4-200 absolute divisor range:
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1 [2..128] [129..64K) [64K..|dividend|/256] >=64K,>|dividend/256|
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udiv 18 22 38 32 30
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sdiv pos: 20 24 41 35 32
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sdiv neg: 15 25 42 36 33
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sh4-300 absolute divisor range:
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8 bit 16 bit 24 bit > 24 bit
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udiv 15 35 28 25
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sdiv 14 36 34 31
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fp-based:
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unsigned: 42 + 3 + 3 (lingering ftrc latency + sts fpul,rx) at caller's site
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signed: 33 + 3 + 3 (lingering ftrc latency + sts fpul,rx) at caller's site
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call-div1: divisor range:
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[1..64K) >= 64K
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unsigned: 63 58
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signed: 76 76
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SFUNC_STATIC call overhead:
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mov.l 0f,r1
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bsrf r1
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SFUNC_GOT call overhead - current:
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mov.l 0f,r1
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mova 0f,r0
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mov.l 1f,r2
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add r1,r0
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mov.l @(r0,r2),r0
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jmp @r0
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; 3 cycles worse than SFUNC_STATIC
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SFUNC_GOT call overhead - improved assembler:
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mov.l 0f,r1
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mova 0f,r0
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mov.l @(r0,r1),r0
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jmp @r0
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; 2 cycles worse than SFUNC_STATIC
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Copyright (C) 2006-2020 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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