a45fe62102
This patch just adds some missing +nosve directives to Advanced SIMD vectorisation tests. gcc/testsuite/ * gcc.target/aarch64/asimd-mull-elem.c: Add +nosve. * gcc.target/aarch64/pr98772.c: Likewise. * gcc.target/aarch64/simd/vect_su_add_sub.c: Likewise.
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/* { dg-do compile } */
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/* { dg-options "-O3" } */
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#pragma GCC target "+nosve"
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typedef int __attribute__ ((mode (SI))) int32_t;
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typedef int __attribute__ ((mode (DI))) int64_t;
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typedef unsigned __attribute__ ((mode (SI))) size_t;
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typedef unsigned __attribute__ ((mode (SI))) uint32_t;
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typedef unsigned __attribute__ ((mode (DI))) uint64_t;
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/* Ensure we use the signed/unsigned extend vectorized add and sub
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instructions. */
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#define N 1024
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int32_t a[N];
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int64_t c[N];
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int64_t d[N];
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uint32_t ua[N];
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uint64_t uc[N];
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uint64_t ud[N];
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void
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add ()
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{
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for (size_t i = 0; i < N; i++)
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d[i] = a[i] + c[i];
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}
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/* { dg-final { scan-assembler-times "\[ \t\]saddw2\[ \t\]+" 1 } } */
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/* { dg-final { scan-assembler-times "\[ \t\]saddw\[ \t\]+" 1 } } */
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void
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subtract ()
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{
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for (size_t i = 0; i < N; i++)
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d[i] = c[i] - a[i];
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}
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/* { dg-final { scan-assembler-times "\[ \t\]ssubw2\[ \t\]+" 1 } } */
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/* { dg-final { scan-assembler-times "\[ \t\]ssubw\[ \t\]+" 1 } } */
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void
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uadd ()
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{
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for (size_t i = 0; i < N; i++)
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ud[i] = ua[i] + uc[i];
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}
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/* { dg-final { scan-assembler-times "\[ \t\]uaddw2\[ \t\]+" 1 } } */
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/* { dg-final { scan-assembler-times "\[ \t\]uaddw\[ \t\]+" 1 } } */
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void
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usubtract ()
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{
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for (size_t i = 0; i < N; i++)
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ud[i] = uc[i] - ua[i];
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}
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/* { dg-final { scan-assembler-times "\[ \t\]usubw2\[ \t\]+" 1 } } */
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/* { dg-final { scan-assembler-times "\[ \t\]usubw\[ \t\]+" 1 } } */
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