4246e0c55b
* mn10300/mn10300.c (expand_epilogue): Restore registers in the
"ret" instruction instead of a separate movm instruction.
Support possible stack deallocation in "ret" instruction too.
* mn10300.md (return_internal): Use "ret" instead of "rets";
restore registers and deallocate stack as needed.
(load_movm): Delete unused pattern.
* mn10300/mn10300.h (SMALL_REGISTER_CLASSES): Define.
From-SVN: r13311
363 lines
8.1 KiB
C
363 lines
8.1 KiB
C
/* Subroutines for insn-output.c for Matsushita MN10300 series
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Copyright (C) 1996 Free Software Foundation, Inc.
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Contributed by Jeff Law (law@cygnus.com).
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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#include "flags.h"
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#include "recog.h"
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#include "expr.h"
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#include "tree.h"
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#include "obstack.h"
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void
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asm_file_start (file)
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FILE *file;
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{
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fprintf (file, "#\tGCC For the Matsushita MN10300\n");
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if (optimize)
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fprintf (file, "# -O%d\n", optimize);
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else
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fprintf (file, "\n\n");
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output_file_directive (file, main_input_filename);
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}
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int
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const_costs (r, c)
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rtx r;
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enum rtx_code c;
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{
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switch (c)
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{
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case CONST_INT:
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if (INT_8_BITS (INTVAL (r)))
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return 0;
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else if (INT_16_BITS (INTVAL (r)))
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return 1;
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else
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return 2;
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case CONST_DOUBLE:
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return 8;
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default:
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return 4;
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}
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}
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/* Print operand X using operand code CODE to assembly language output file
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FILE. */
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void
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print_operand (file, x, code)
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FILE *file;
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rtx x;
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int code;
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{
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switch (code)
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{
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case 'b':
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case 'B':
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/* These are normal and reversed branches. */
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switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
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{
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case NE:
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fprintf (file, "ne");
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break;
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case EQ:
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fprintf (file, "eq");
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break;
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case GE:
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fprintf (file, "ge");
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break;
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case GT:
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fprintf (file, "gt");
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break;
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case LE:
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fprintf (file, "le");
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break;
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case LT:
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fprintf (file, "lt");
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break;
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case GEU:
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fprintf (file, "cc");
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break;
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case GTU:
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fprintf (file, "hi");
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break;
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case LEU:
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fprintf (file, "ls");
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break;
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case LTU:
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fprintf (file, "cs");
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break;
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default:
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abort ();
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}
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break;
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case 'C':
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/* This is used for the operand to a call instruction;
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if it's a REG, enclose it in parens, else output
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the operand normally. */
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if (GET_CODE (x) == REG)
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{
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fputc ('(', file);
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print_operand (file, x, 0);
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fputc (')', file);
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}
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else
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print_operand (file, x, 0);
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break;
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default:
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switch (GET_CODE (x))
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{
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case MEM:
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fputc ('(', file);
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output_address (XEXP (x, 0));
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fputc (')', file);
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break;
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case REG:
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fprintf (file, "%s", reg_names[REGNO (x)]);
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break;
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case SUBREG:
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fprintf (file, "%s",
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reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
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break;
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case CONST_INT:
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case SYMBOL_REF:
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case CONST:
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case LABEL_REF:
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case CODE_LABEL:
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print_operand_address (file, x);
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break;
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default:
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abort ();
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}
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break;
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}
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}
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/* Output assembly language output for the address ADDR to FILE. */
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void
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print_operand_address (file, addr)
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FILE *file;
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rtx addr;
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{
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switch (GET_CODE (addr))
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{
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case REG:
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if (addr == stack_pointer_rtx)
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print_operand_address (file, gen_rtx (PLUS, SImode,
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stack_pointer_rtx,
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GEN_INT (0)));
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else
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print_operand (file, addr, 0);
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break;
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case PLUS:
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{
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rtx base, index;
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if (REG_P (XEXP (addr, 0))
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&& REG_OK_FOR_BASE_P (XEXP (addr, 0)))
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base = XEXP (addr, 0), index = XEXP (addr, 1);
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else if (REG_P (XEXP (addr, 1))
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&& REG_OK_FOR_BASE_P (XEXP (addr, 1)))
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base = XEXP (addr, 1), index = XEXP (addr, 0);
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else
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abort ();
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print_operand (file, index, 0);
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fputc (',', file);
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print_operand (file, base, 0);;
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break;
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}
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case SYMBOL_REF:
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output_addr_const (file, addr);
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break;
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default:
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output_addr_const (file, addr);
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break;
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}
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}
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void
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expand_prologue ()
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{
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unsigned int size = get_frame_size ();
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/* For simplicity, we just movm all the callee saved registers to
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the stack with one instruction, then set up the frame pointer
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(if needed), and finally allocate the new stack. */
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emit_insn (gen_store_movm ());
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if (frame_pointer_needed)
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{
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emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
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emit_insn (gen_addsi3 (frame_pointer_rtx,
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frame_pointer_rtx,
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GEN_INT (20)));
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}
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if (size)
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-size)));
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}
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void
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expand_epilogue ()
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{
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unsigned int size = get_frame_size ();
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/* Cut back the stack. */
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if (frame_pointer_needed)
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{
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emit_insn (gen_addsi3 (frame_pointer_rtx,
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frame_pointer_rtx,
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GEN_INT (-20)));
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emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
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size = 0;
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}
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else if (size > 255)
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{
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (size)));
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size = 0;
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}
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/* Deallocate remaining stack, restore registers and return. And return. */
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emit_jump_insn (gen_return_internal (GEN_INT (size)));
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}
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/* Update the condition code from the insn. */
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void
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notice_update_cc (body, insn)
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rtx body;
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rtx insn;
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{
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#if 0
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switch (get_attr_cc (insn))
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{
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case CC_NONE:
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/* Insn does not affect CC at all. */
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break;
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case CC_NONE_0HIT:
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/* Insn does not change CC, but the 0'th operand has been changed. */
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if (cc_status.value1 != 0
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&& reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
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cc_status.value1 = 0;
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break;
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case CC_SET_ZN_C0:
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/* Insn sets the Z,N flags of CC to recog_operand[0].
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V is always set to 0. C may or may not be set to 0 but that's ok
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because alter_cond will change tests to use EQ/NE. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_NO_OVERFLOW;
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cc_status.value1 = recog_operand[0];
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break;
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case CC_SET:
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case CC_COMPARE:
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/* The insn is a compare instruction. */
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CC_STATUS_INIT;
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cc_status.value1 = SET_SRC (body);
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break;
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case CC_CLOBBER:
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/* Insn doesn't leave CC in a usable state. */
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CC_STATUS_INIT;
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break;
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}
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#endif
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CC_STATUS_INIT;
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}
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/* Return true if OP is a valid call operand. */
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int
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call_address_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
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}
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/* What (if any) secondary registers are needed to move IN with mode
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MODE into a register from in register class CLASS.
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We might be able to simplify this. */
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enum reg_class
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secondary_reload_class (class, mode, in)
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enum reg_class class;
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enum machine_mode mode;
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rtx in;
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{
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int regno;
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/* Memory loads less than a full word wide can't have an
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address or stack pointer destination. They must use
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a data register as an intermediate register. */
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if (GET_CODE (in) == MEM
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&& (mode == QImode || mode == HImode)
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&& (class == ADDRESS_REGS || class == SP_REGS))
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return DATA_REGS;
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/* We can't directly load sp + const_int into a data register;
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we must use an address register as an intermediate. */
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if (class == DATA_REGS
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&& (in == stack_pointer_rtx
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|| (GET_CODE (in) == PLUS
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&& XEXP (in, 0) == stack_pointer_rtx)))
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return ADDRESS_REGS;
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/* Get the true register. */
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if (GET_CODE (in) == REG)
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{
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regno = REGNO (in);
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if (regno >= FIRST_PSEUDO_REGISTER)
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regno = true_regnum (in);
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}
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/* We can't copy directly from a data register into the stack
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pointer. */
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if (class == SP_REGS
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&& GET_CODE (in) == REG
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&& regno < 4)
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return ADDRESS_REGS;
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/* Otherwise assume no secondary reloads are needed. */
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return NO_REGS;
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}
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