694 lines
24 KiB
C++
694 lines
24 KiB
C++
/* Definitions of target machine for GNU compiler.
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Matsushita MN10300 series
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Copyright (C) 1996-2021 Free Software Foundation, Inc.
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Contributed by Jeff Law (law@cygnus.com).
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#undef ASM_SPEC
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#undef LIB_SPEC
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#undef ENDFILE_SPEC
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#undef LINK_SPEC
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#define LINK_SPEC "%{mrelax:%{!r:--relax}}"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}"
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/* Names to predefine in the preprocessor for this target machine. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define ("__mn10300__"); \
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builtin_define ("__MN10300__"); \
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builtin_assert ("cpu=mn10300"); \
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builtin_assert ("machine=mn10300"); \
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\
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if (TARGET_AM34) \
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{ \
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builtin_define ("__AM33__=4"); \
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builtin_define ("__AM34__"); \
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} \
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else if (TARGET_AM33_2) \
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{ \
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builtin_define ("__AM33__=2"); \
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builtin_define ("__AM33_2__"); \
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} \
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else if (TARGET_AM33) \
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builtin_define ("__AM33__=1"); \
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\
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builtin_define (TARGET_ALLOW_LIW ? \
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"__LIW__" : "__NO_LIW__");\
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\
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builtin_define (TARGET_ALLOW_SETLB ? \
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"__SETLB__" : "__NO_SETLB__");\
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} \
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while (0)
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#ifndef MN10300_OPTS_H
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#include "config/mn10300/mn10300-opts.h"
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#endif
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extern enum processor_type mn10300_tune_cpu;
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#define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33)
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#define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2)
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#define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34)
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#ifndef PROCESSOR_DEFAULT
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#define PROCESSOR_DEFAULT PROCESSOR_MN10300
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#endif
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/* Target machine storage layout */
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/* Define this if most significant bit is lowest numbered
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in instructions that operate on numbered bit-fields.
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This is not true on the Matsushita MN1003. */
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#define BITS_BIG_ENDIAN 0
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/* Define this if most significant byte of a word is the lowest numbered. */
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/* This is not true on the Matsushita MN10300. */
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#define BYTES_BIG_ENDIAN 0
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/* Define this if most significant word of a multiword number is lowest
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numbered.
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This is not true on the Matsushita MN10300. */
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#define WORDS_BIG_ENDIAN 0
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/* Width of a word, in units (bytes). */
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#define UNITS_PER_WORD 4
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/* Allocation boundary (in *bits*) for storing arguments in argument list. */
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#define PARM_BOUNDARY 32
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/* The stack goes in 32-bit lumps. */
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#define STACK_BOUNDARY 32
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/* Allocation boundary (in *bits*) for the code of a function.
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8 is the minimum boundary; it's unclear if bigger alignments
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would improve performance. */
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#define FUNCTION_BOUNDARY 8
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/* No data type wants to be aligned rounder than this. */
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#define BIGGEST_ALIGNMENT 32
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/* Alignment of field after `int : 0' in a structure. */
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#define EMPTY_FIELD_BOUNDARY 32
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/* Define this if move instructions will actually fail to work
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when given unaligned data. */
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#define STRICT_ALIGNMENT 1
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/* Define this as 1 if `char' should by default be signed; else as 0. */
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#define DEFAULT_SIGNED_CHAR 0
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#undef SIZE_TYPE
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#define SIZE_TYPE "unsigned int"
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#undef PTRDIFF_TYPE
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#define PTRDIFF_TYPE "int"
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#undef WCHAR_TYPE
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#define WCHAR_TYPE "long int"
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#undef WCHAR_TYPE_SIZE
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#define WCHAR_TYPE_SIZE BITS_PER_WORD
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/* Standard register usage. */
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/* Number of actual hardware registers.
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The hardware registers are assigned numbers for the compiler
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from 0 to just below FIRST_PSEUDO_REGISTER.
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers. */
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#define FIRST_PSEUDO_REGISTER 52
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/* Specify machine-specific register numbers. The commented out entries
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are defined in mn10300.md. */
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#define FIRST_DATA_REGNUM 0
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#define LAST_DATA_REGNUM 3
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#define FIRST_ADDRESS_REGNUM 4
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/* #define PIC_REG 6 */
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#define LAST_ADDRESS_REGNUM 8
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/* #define SP_REG 9 */
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#define FIRST_EXTENDED_REGNUM 10
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#define LAST_EXTENDED_REGNUM 17
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#define FIRST_FP_REGNUM 18
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#define LAST_FP_REGNUM 49
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/* #define MDR_REG 50 */
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/* #define CC_REG 51 */
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#define FIRST_ARGUMENT_REGNUM 0
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1)
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1)
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/* Base register for access to arguments of the function. This
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is a fake register and will be eliminated into either the frame
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pointer or stack pointer. */
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#define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM
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/* Register in which static-chain is passed to a function. */
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#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1)
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator. */
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#define FIXED_REGISTERS \
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{ 0, 0, 0, 0, /* data regs */ \
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0, 0, 0, 0, /* addr regs */ \
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1, /* arg reg */ \
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1, /* sp reg */ \
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0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \
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0, 0, /* fp regs (18-19) */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \
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0, /* mdr reg */ \
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1 /* cc reg */ \
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}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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registers that can be used without being saved.
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The latter must include the registers where values are returned
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and the register where structure-value addresses are passed.
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Aside from that, you can include as many other registers as you
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like. */
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#define CALL_REALLY_USED_REGISTERS \
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{ 1, 1, 0, 0, /* data regs */ \
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1, 1, 0, 0, /* addr regs */ \
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1, /* arg reg */ \
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1, /* sp reg */ \
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1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \
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1, 1, /* fp regs (18-19) */ \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \
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1, /* mdr reg */ \
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1 /* cc reg */ \
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}
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#define REG_ALLOC_ORDER \
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{ 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
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, 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
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, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \
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}
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/* 4 data, and effectively 3 address registers is small as far as I'm
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concerned. */
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#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
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/* Define the classes of registers for register constraints in the
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machine description. Also define ranges of constants.
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One of the classes must always be named ALL_REGS and include all hard regs.
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If there is more than one class, another class must be named NO_REGS
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and contain no registers.
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The name GENERAL_REGS must be the name of a class (or an alias for
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another name such as ALL_REGS). This is the class of registers
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that is allowed by "g" or "r" in a register constraint.
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Also, registers outside this class are allocated only when
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instructions express preferences for them.
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The classes must be numbered in nondecreasing order; that is,
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a larger-numbered class must never be contained completely
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in a smaller-numbered class.
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For any two classes, it is very desirable that there be another
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class that represents their union. */
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enum reg_class
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{
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NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS,
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EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS,
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GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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/* Give names of register classes as strings for dump file. */
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \
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"EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \
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"GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
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}
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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of length N_REG_CLASSES. */
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#define REG_CLASS_CONTENTS \
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{ { 0, 0 }, /* No regs */ \
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{ 0x0000000f, 0 }, /* DATA_REGS */ \
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{ 0x000001f0, 0 }, /* ADDRESS_REGS */ \
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{ 0x00000200, 0 }, /* SP_REGS */ \
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{ 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \
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{ 0x0003fc00, 0 }, /* EXTENDED_REGS */ \
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{ 0xfffc0000, 0x3ffff },/* FP_REGS */ \
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{ 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
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{ 0x00000000, 0x80000 },/* CC_REGS */ \
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{ 0x00000000, 0x40000 },/* MDR_REGS */ \
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{ 0x0003fdff, 0 }, /* GENERAL_REGS */ \
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{ 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \
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{ 0xffffffff, 0xfffff } /* ALL_REGS */ \
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}
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/* The same information, inverted:
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Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array. */
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \
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(REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \
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(REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
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(REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
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(REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
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(REGNO) == MDR_REG ? MDR_REGS : \
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(REGNO) == CC_REG ? CC_REGS : \
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NO_REGS)
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/* The class value for index registers, and the one for base regs. */
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#define INDEX_REG_CLASS \
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(TARGET_AM33 ? GENERAL_REGS : DATA_REGS)
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#define BASE_REG_CLASS \
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(TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS)
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/* Macros to check register numbers against specific register classes. */
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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and check its validity for a certain class.
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We have two alternate definitions for each of them.
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The usual definition accepts all pseudo regs; the other rejects
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them unless they have been allocated suitable hard regs.
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The symbol REG_OK_STRICT causes the latter definition to be used.
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Most source files want to accept pseudo regs in the hope that
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they will get allocated to the class that the insn wants them to be in.
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Source files for reload pass need to be strict.
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After reload, it makes no difference, since pseudo regs have
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been eliminated by then. */
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/* These assume that REGNO is a hard or pseudo reg number.
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They give nonzero only if REGNO is a hard reg of the suitable class
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or a pseudo reg currently allocated to a suitable hard reg.
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Since they use reg_renumber, they are safe only once reg_renumber
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has been allocated, which happens in reginfo.c during register
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allocation. */
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#ifndef REG_OK_STRICT
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# define REG_STRICT 0
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#else
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# define REG_STRICT 1
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#endif
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#define REGNO_DATA_P(regno, strict) \
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mn10300_regno_in_class_p (regno, DATA_REGS, strict)
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#define REGNO_ADDRESS_P(regno, strict) \
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mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
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#define REGNO_EXTENDED_P(regno, strict) \
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mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict)
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#define REGNO_GENERAL_P(regno, strict) \
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mn10300_regno_in_class_p (regno, GENERAL_REGS, strict)
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#define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \
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mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict)
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#define REGNO_OK_FOR_BASE_P(regno) \
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(REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT))
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#define REG_OK_FOR_BASE_P(X) \
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(REGNO_OK_FOR_BASE_P (REGNO (X)))
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#define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \
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mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
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#define REGNO_OK_FOR_BIT_BASE_P(regno) \
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(REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT))
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#define REG_OK_FOR_BIT_BASE_P(X) \
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(REGNO_OK_FOR_BIT_BASE_P (REGNO (X)))
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#define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \
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mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict)
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#define REGNO_OK_FOR_INDEX_P(regno) \
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(REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT))
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#define REG_OK_FOR_INDEX_P(X) \
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(REGNO_OK_FOR_INDEX_P (REGNO (X)))
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#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
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(!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
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/* A class that contains registers which the compiler must always
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access in a mode that is the same size as the mode in which it
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loaded the register. */
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#define CLASS_CANNOT_CHANGE_SIZE FP_REGS
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/* Return 1 if VALUE is in the range specified. */
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#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
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#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
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/* Stack layout; function entry, exit and calling. */
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/* Define this if pushing a word on the stack
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makes the stack pointer a smaller address. */
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#define STACK_GROWS_DOWNWARD 1
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/* Define this to nonzero if the nominal address of the stack frame
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is at the high-address end of the local variables;
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that is, each additional local variable allocated
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goes at a more negative offset in the frame. */
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#define FRAME_GROWS_DOWNWARD 1
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/* Offset of first parameter from the argument pointer register value. */
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/* Is equal to the size of the saved fp + pc, even if an fp isn't
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saved since the value is used before we know. */
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#define FIRST_PARM_OFFSET(FNDECL) 4
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/* But the CFA is at the arg pointer directly, not at the first argument. */
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#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
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#define ELIMINABLE_REGS \
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{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
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{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
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#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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OFFSET = mn10300_initial_offset (FROM, TO)
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/* We use d0/d1 for passing parameters, so allocate 8 bytes of space
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for a register flushback area. */
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#define REG_PARM_STACK_SPACE(DECL) 8
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#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
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#define ACCUMULATE_OUTGOING_ARGS 1
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/* So we can allocate space for return pointers once for the function
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instead of around every call. */
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#define STACK_POINTER_OFFSET 4
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/* 1 if N is a possible register number for function argument passing.
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On the MN10300, d0 and d1 are used in this way. */
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#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
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/* Define a data type for recording info about an argument list
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during the scan of that argument list. This data type should
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hold all necessary information about the function itself
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and about the args processed so far, enough to enable macros
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such as FUNCTION_ARG to determine where the next arg should go.
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On the MN10300, this is a single integer, which is a number of bytes
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of arguments scanned so far. */
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#define CUMULATIVE_ARGS struct cum_arg
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struct cum_arg
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{
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int nbytes;
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};
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/* Initialize a variable CUM of type CUMULATIVE_ARGS
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for a call to a function whose data type is FNTYPE.
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For a library call, FNTYPE is 0.
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On the MN10300, the offset starts at 0. */
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#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
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((CUM).nbytes = 0)
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#define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N)
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#define DEFAULT_PCC_STRUCT_RETURN 0
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/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
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the stack pointer does not matter. The value is tested only in
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functions that have frame pointers.
|
||
No definition is equivalent to always zero. */
|
||
|
||
#define EXIT_IGNORE_STACK 1
|
||
|
||
/* Output assembler code to FILE to increment profiler label # LABELNO
|
||
for profiling a function entry. */
|
||
|
||
#define FUNCTION_PROFILER(FILE, LABELNO) ;
|
||
|
||
/* Length in units of the trampoline for entering a nested function. */
|
||
|
||
#define TRAMPOLINE_SIZE 16
|
||
#define TRAMPOLINE_ALIGNMENT 32
|
||
|
||
/* A C expression whose value is RTL representing the value of the return
|
||
address for the frame COUNT steps up from the current frame.
|
||
|
||
On the mn10300, the return address is not at a constant location
|
||
due to the frame layout. Luckily, it is at a constant offset from
|
||
the argument pointer, so we define RETURN_ADDR_RTX to return a
|
||
MEM using arg_pointer_rtx. Reload will replace arg_pointer_rtx
|
||
with a reference to the stack/frame pointer + an appropriate offset. */
|
||
|
||
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
||
((COUNT == 0) \
|
||
? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
|
||
: (rtx) 0)
|
||
|
||
/* The return address is saved both in the stack and in MDR. Using
|
||
the stack location is handiest for what unwinding needs. */
|
||
#define INCOMING_RETURN_ADDR_RTX \
|
||
gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM))
|
||
|
||
/* Maximum number of registers that can appear in a valid memory address. */
|
||
|
||
#define MAX_REGS_PER_ADDRESS 2
|
||
|
||
|
||
/* We have post-increments. */
|
||
#define HAVE_POST_INCREMENT TARGET_AM33
|
||
#define HAVE_POST_MODIFY_DISP TARGET_AM33
|
||
|
||
/* ... But we don't want to use them for block moves. Small offsets are
|
||
just as effective, at least for inline block move sizes, and appears
|
||
to produce cleaner code. */
|
||
#define USE_LOAD_POST_INCREMENT(M) 0
|
||
#define USE_STORE_POST_INCREMENT(M) 0
|
||
|
||
/* Accept either REG or SUBREG where a register is valid. */
|
||
|
||
#define RTX_OK_FOR_BASE_P(X, strict) \
|
||
((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \
|
||
(strict))) \
|
||
|| (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
|
||
&& REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \
|
||
(strict))))
|
||
|
||
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
|
||
do { \
|
||
rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
|
||
if (new_x) \
|
||
{ \
|
||
X = new_x; \
|
||
goto WIN; \
|
||
} \
|
||
} while (0)
|
||
|
||
|
||
/* Zero if this needs fixing up to become PIC. */
|
||
|
||
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
||
mn10300_legitimate_pic_operand_p (X)
|
||
|
||
/* Register to hold the addressing base for
|
||
position independent code access to data items. */
|
||
#define PIC_OFFSET_TABLE_REGNUM PIC_REG
|
||
|
||
/* The name of the pseudo-symbol representing the Global Offset Table. */
|
||
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
|
||
|
||
#define SYMBOLIC_CONST_P(X) \
|
||
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
|
||
&& ! LEGITIMATE_PIC_OPERAND_P (X))
|
||
|
||
/* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */
|
||
#define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X))
|
||
|
||
#define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y)
|
||
#define REVERSIBLE_CC_MODE(MODE) 0
|
||
|
||
/* Nonzero if access to memory by bytes or half words is no faster
|
||
than accessing full words. */
|
||
#define SLOW_BYTE_ACCESS 1
|
||
|
||
#define NO_FUNCTION_CSE 1
|
||
|
||
/* According expr.c, a value of around 6 should minimize code size, and
|
||
for the MN10300 series, that's our primary concern. */
|
||
#define MOVE_RATIO(speed) 6
|
||
|
||
#define TEXT_SECTION_ASM_OP "\t.section .text"
|
||
#define DATA_SECTION_ASM_OP "\t.section .data"
|
||
#define BSS_SECTION_ASM_OP "\t.section .bss"
|
||
|
||
#define ASM_COMMENT_START "#"
|
||
|
||
/* Output to assembler file text saying following lines
|
||
may contain character constants, extra white space, comments, etc. */
|
||
|
||
#define ASM_APP_ON "#APP\n"
|
||
|
||
/* Output to assembler file text saying following lines
|
||
no longer contain unusual constructs. */
|
||
|
||
#define ASM_APP_OFF "#NO_APP\n"
|
||
|
||
#undef USER_LABEL_PREFIX
|
||
#define USER_LABEL_PREFIX "_"
|
||
|
||
/* This says how to output the assembler to define a global
|
||
uninitialized but not common symbol.
|
||
Try to use asm_output_bss to implement this macro. */
|
||
|
||
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
||
asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
|
||
|
||
/* Globalizing directive for a label. */
|
||
#define GLOBAL_ASM_OP "\t.global "
|
||
|
||
/* This is how to output a reference to a user-level label named NAME.
|
||
`assemble_name' uses this. */
|
||
|
||
#undef ASM_OUTPUT_LABELREF
|
||
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
|
||
asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME))
|
||
|
||
/* This is how we tell the assembler that two symbols have the same value. */
|
||
|
||
#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
|
||
do \
|
||
{ \
|
||
assemble_name (FILE, NAME1); \
|
||
fputs (" = ", FILE); \
|
||
assemble_name (FILE, NAME2); \
|
||
fputc ('\n', FILE); \
|
||
} \
|
||
while (0)
|
||
|
||
/* How to refer to registers in assembler output.
|
||
This sequence is indexed by compiler's hard-register-number (see above). */
|
||
|
||
#define REGISTER_NAMES \
|
||
{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
|
||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \
|
||
, "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \
|
||
, "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \
|
||
, "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \
|
||
, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \
|
||
, "mdr", "EPSW" \
|
||
}
|
||
|
||
#define ADDITIONAL_REGISTER_NAMES \
|
||
{ {"r8", 4}, {"r9", 5}, {"r10", 6}, {"r11", 7}, \
|
||
{"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \
|
||
{"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \
|
||
{"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \
|
||
, {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \
|
||
, {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \
|
||
, {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \
|
||
, {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \
|
||
, {"cc", CC_REG} \
|
||
}
|
||
|
||
/* Print an instruction operand X on file FILE.
|
||
look in mn10300.c for details */
|
||
|
||
#define PRINT_OPERAND(FILE, X, CODE) \
|
||
mn10300_print_operand (FILE, X, CODE)
|
||
|
||
/* Print a memory operand whose address is X, on file FILE.
|
||
This uses a function in output-vax.c. */
|
||
|
||
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
|
||
mn10300_print_operand_address (FILE, ADDR)
|
||
|
||
/* This is how to output an element of a case-vector that is absolute. */
|
||
|
||
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
||
fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
|
||
|
||
/* This is how to output an element of a case-vector that is relative. */
|
||
|
||
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
||
fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
|
||
|
||
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
||
if ((LOG) != 0) \
|
||
fprintf (FILE, "\t.align %d\n", (LOG))
|
||
|
||
/* We don't have to worry about dbx compatibility for the mn10300. */
|
||
#define DEFAULT_GDB_EXTENSIONS 1
|
||
|
||
/* Use dwarf2 debugging info by default. */
|
||
#undef PREFERRED_DEBUGGING_TYPE
|
||
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
||
#define DWARF2_DEBUGGING_INFO 1
|
||
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
||
|
||
/* Specify the machine mode that this machine uses
|
||
for the index in the tablejump instruction. */
|
||
#define CASE_VECTOR_MODE Pmode
|
||
|
||
/* Define if operations between registers always perform the operation
|
||
on the full register even if a narrower mode is specified. */
|
||
#define WORD_REGISTER_OPERATIONS 1
|
||
|
||
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
||
|
||
/* Max number of bytes we can move from memory to memory
|
||
in one reasonably fast instruction. */
|
||
#define MOVE_MAX 4
|
||
|
||
/* Define if shifts truncate the shift count
|
||
which implies one can omit a sign-extension or zero-extension
|
||
of a shift count. */
|
||
#define SHIFT_COUNT_TRUNCATED 1
|
||
|
||
/* Specify the machine mode that pointers have.
|
||
After generation of rtl, the compiler makes no further distinction
|
||
between pointers and any other objects of this machine mode. */
|
||
#define Pmode SImode
|
||
|
||
/* A function address in a call instruction
|
||
is a byte address (for indexing purposes)
|
||
so give the MEM rtx a byte's mode. */
|
||
#define FUNCTION_MODE QImode
|
||
|
||
/* The assembler op to get a word. */
|
||
|
||
#define FILE_ASM_OP "\t.file\n"
|
||
|