Iain Buclaw 433b6b12df d: Define IN_TARGET_CODE in all machine-specific D language files. ... This is to be consistent with the rest of the back-end. gcc/ChangeLog: * config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define. * config/arm/arm-d.c (IN_TARGET_CODE): Likewise. * config/i386/i386-d.c (IN_TARGET_CODE): Likewise. * config/mips/mips-d.c (IN_TARGET_CODE): Likewise. * config/pa/pa-d.c (IN_TARGET_CODE): Likewise. * config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise. * config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise. * config/s390/s390-d.c (IN_TARGET_CODE): Likewise. * config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.		2021-03-26 16:14:18 +01:00
..
arch-canonicalize
constraints.md
elf.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
freebsd.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
generic.md
linux.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
multilib-generator
peephole.md
pic.md
predicates.md	RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md	2021-03-23 17:32:41 +08:00
riscv-builtins.c
riscv-c.c
riscv-cores.def
riscv-d.c	d: Define IN_TARGET_CODE in all machine-specific D language files.	2021-03-26 16:14:18 +01:00
riscv-ftypes.def
riscv-modes.def
riscv-opts.h
riscv-passes.def
riscv-protos.h
riscv-shorten-memrefs.c
riscv-sr.c
riscv-subset.h
riscv.c	RISC-V: Fix riscv_subword() for big endian	2021-03-23 17:32:41 +08:00
riscv.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
riscv.md	RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md	2021-03-23 17:32:41 +08:00
riscv.opt	RISC-V: Support -mlittle-endian and -mbig-endian	2021-03-23 17:31:13 +08:00
rtems.h
sifive-7.md
sync.md
t-elf-multilib
t-linux
t-linux-multilib
t-riscv
t-rtems
t-withmultilib
t-withmultilib-generator