484 lines
8.4 KiB
NASM
484 lines
8.4 KiB
NASM
/* Copyright (C) 1994 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file with other programs, and to distribute
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those programs without any restriction coming from the use of this
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file. (The General Public License restrictions do apply in other
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respects; for example, they cover modification of the file, and
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distribution when not linked into another program.)
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* As a special exception, if you link this library with other files,
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some of which are compiled with GCC, to produce an executable,
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this library does not by itself cause the resulting executable
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to be covered by the GNU General Public License.
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This exception does not however invalidate any other reasons why
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the executable file might be covered by the GNU General Public License. */
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!! libgcc1 routines for the Hitachi SH cpu.
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!! Contributed by Steve Chamberlain.
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!! sac@cygnus.com
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#ifdef L_ashiftrt
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.global ___ashiftrt_r4_0
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.global ___ashiftrt_r4_1
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.global ___ashiftrt_r4_2
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.global ___ashiftrt_r4_3
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.global ___ashiftrt_r4_4
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.global ___ashiftrt_r4_5
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.global ___ashiftrt_r4_6
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.global ___ashiftrt_r4_7
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.global ___ashiftrt_r4_8
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.global ___ashiftrt_r4_9
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.global ___ashiftrt_r4_10
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.global ___ashiftrt_r4_11
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.global ___ashiftrt_r4_12
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.global ___ashiftrt_r4_13
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.global ___ashiftrt_r4_14
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.global ___ashiftrt_r4_15
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.global ___ashiftrt_r4_16
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.global ___ashiftrt_r4_17
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.global ___ashiftrt_r4_18
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.global ___ashiftrt_r4_19
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.global ___ashiftrt_r4_20
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.global ___ashiftrt_r4_21
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.global ___ashiftrt_r4_22
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.global ___ashiftrt_r4_23
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.global ___ashiftrt_r4_24
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.global ___ashiftrt_r4_25
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.global ___ashiftrt_r4_26
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.global ___ashiftrt_r4_27
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.global ___ashiftrt_r4_28
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.global ___ashiftrt_r4_29
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.global ___ashiftrt_r4_30
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.global ___ashiftrt_r4_31
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.global ___ashiftrt_r4_32
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___ashiftrt_r4_32:
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shar r4
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___ashiftrt_r4_31:
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shar r4
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___ashiftrt_r4_30:
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shar r4
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___ashiftrt_r4_29:
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shar r4
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___ashiftrt_r4_28:
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shar r4
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___ashiftrt_r4_27:
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shar r4
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___ashiftrt_r4_26:
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shar r4
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___ashiftrt_r4_25:
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shar r4
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___ashiftrt_r4_24:
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shar r4
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___ashiftrt_r4_23:
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shar r4
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___ashiftrt_r4_22:
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shar r4
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___ashiftrt_r4_21:
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shar r4
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___ashiftrt_r4_20:
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shar r4
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___ashiftrt_r4_19:
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shar r4
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___ashiftrt_r4_18:
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shar r4
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___ashiftrt_r4_17:
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shar r4
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___ashiftrt_r4_16:
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shar r4
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___ashiftrt_r4_15:
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shar r4
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___ashiftrt_r4_14:
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shar r4
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___ashiftrt_r4_13:
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shar r4
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___ashiftrt_r4_12:
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shar r4
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___ashiftrt_r4_11:
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shar r4
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___ashiftrt_r4_10:
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shar r4
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___ashiftrt_r4_9:
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shar r4
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___ashiftrt_r4_8:
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shar r4
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___ashiftrt_r4_7:
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shar r4
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___ashiftrt_r4_6:
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shar r4
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___ashiftrt_r4_5:
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shar r4
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___ashiftrt_r4_4:
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shar r4
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___ashiftrt_r4_3:
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shar r4
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___ashiftrt_r4_2:
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shar r4
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___ashiftrt_r4_1:
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rts
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shar r4
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___ashiftrt_r4_0:
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rts
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nop
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#endif
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#ifdef L_movstr
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.text
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! done all the large groups, do the remainder
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! jump to movstr+
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done:
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add #64,r5
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mova ___movstrSI0,r0
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shll2 r6
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add r6,r0
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jmp @r0
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add #64,r4
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.align 4
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.global ___movstrSI64
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___movstrSI64:
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mov.l @(60,r5),r0
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mov.l r0,@(60,r4)
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.global ___movstrSI60
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___movstrSI60:
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mov.l @(56,r5),r0
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mov.l r0,@(56,r4)
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.global ___movstrSI56
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___movstrSI56:
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mov.l @(52,r5),r0
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mov.l r0,@(52,r4)
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.global ___movstrSI52
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___movstrSI52:
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mov.l @(48,r5),r0
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mov.l r0,@(48,r4)
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.global ___movstrSI48
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___movstrSI48:
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mov.l @(44,r5),r0
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mov.l r0,@(44,r4)
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.global ___movstrSI44
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___movstrSI44:
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mov.l @(40,r5),r0
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mov.l r0,@(40,r4)
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.global ___movstrSI40
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___movstrSI40:
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mov.l @(36,r5),r0
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mov.l r0,@(36,r4)
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.global ___movstrSI36
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___movstrSI36:
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mov.l @(32,r5),r0
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mov.l r0,@(32,r4)
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.global ___movstrSI32
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___movstrSI32:
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mov.l @(28,r5),r0
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mov.l r0,@(28,r4)
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.global ___movstrSI28
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___movstrSI28:
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mov.l @(24,r5),r0
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mov.l r0,@(24,r4)
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.global ___movstrSI24
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___movstrSI24:
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mov.l @(20,r5),r0
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mov.l r0,@(20,r4)
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.global ___movstrSI20
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___movstrSI20:
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mov.l @(16,r5),r0
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mov.l r0,@(16,r4)
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.global ___movstrSI16
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___movstrSI16:
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mov.l @(12,r5),r0
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mov.l r0,@(12,r4)
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.global ___movstrSI12
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___movstrSI12:
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mov.l @(8,r5),r0
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mov.l r0,@(8,r4)
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.global ___movstrSI8
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___movstrSI8:
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mov.l @(4,r5),r0
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mov.l r0,@(4,r4)
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.global ___movstrSI4
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___movstrSI4:
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mov.l @(0,r5),r0
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mov.l r0,@(0,r4)
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___movstrSI0:
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rts
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or r0,r0,r0
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.align 4
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.global ___movstr
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___movstr:
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mov.l @(60,r5),r0
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mov.l r0,@(60,r4)
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mov.l @(56,r5),r0
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mov.l r0,@(56,r4)
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mov.l @(52,r5),r0
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mov.l r0,@(52,r4)
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mov.l @(48,r5),r0
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mov.l r0,@(48,r4)
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mov.l @(44,r5),r0
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mov.l r0,@(44,r4)
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mov.l @(40,r5),r0
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mov.l r0,@(40,r4)
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mov.l @(36,r5),r0
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mov.l r0,@(36,r4)
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mov.l @(32,r5),r0
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mov.l r0,@(32,r4)
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mov.l @(28,r5),r0
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mov.l r0,@(28,r4)
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mov.l @(24,r5),r0
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mov.l r0,@(24,r4)
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mov.l @(20,r5),r0
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mov.l r0,@(20,r4)
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mov.l @(16,r5),r0
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mov.l r0,@(16,r4)
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mov.l @(12,r5),r0
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mov.l r0,@(12,r4)
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mov.l @(8,r5),r0
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mov.l r0,@(8,r4)
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mov.l @(4,r5),r0
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mov.l r0,@(4,r4)
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mov.l @(0,r5),r0
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mov.l r0,@(0,r4)
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add #-16,r6
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cmp/pl r6
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bf done
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add #64,r5
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bra ___movstr
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add #64,r4
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#endif
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#ifdef L_mulsi3
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.global ___mulsi3
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! r4 = aabb
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! r5 = ccdd
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! r0 = aabb*ccdd via partial products
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!
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! if aa == 0 and cc = 0
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! r0 = bb*dd
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!
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! else
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! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
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!
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___mulsi3:
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mulu r4,r5 ! multiply the lsws macl=bb*dd
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mov r5,r3 ! r3 = ccdd
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swap.w r4,r2 ! r2 = bbaa
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xtrct r2,r3 ! r3 = aacc
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tst r3,r3 ! msws zero ?
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bf hiset
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rts ! yes - then weve got the answer
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sts macl,r0
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hiset: sts macl,r0 ! r0 = bb*dd
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mulu r2,r5 | brewing macl = aa*dd
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sts macl,r1
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mulu r3,r4 | brewing macl = cc*bb
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sts macl,r2
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add r1,r2
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shll16 r2
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rts
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add r2,r0
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#endif
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#ifdef L_sdivsi3
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.title "SH DIVIDE"
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!! 4 byte integer Divide code for the Hitachi SH
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!!
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!! Steve Chamberlain
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!! sac@cygnus.com
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!!
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!!
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!! args in r4 and r5, result in r0 clobber r1,r2,r3
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.global ___sdivsi3
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___sdivsi3:
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mov r4,r1
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mov r5,r0
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tst r0,r0
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bt div0
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mov #0,r2
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div0s r2,r1
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subc r3,r3
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subc r2,r1
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div0s r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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addc r2,r1
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rts
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mov r1,r0
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div0: rts
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mov #0,r0
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#endif
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#ifdef L_udivsi3
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.title "SH DIVIDE"
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!! 4 byte integer Divide code for the Hitachi SH
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!!
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!! Steve Chamberlain
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!! sac@cygnus.com
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!!
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!!
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!! args in r4 and r5, result in r0, clobbers r4,r6, pr and t bit
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.global ___udivsi3
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___udivsi3:
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longway:
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mov #0,r0
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div0u
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! get one bit from the msb of the numerator into the T
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! bit and divide it by whats in r5. Put the answer bit
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! into the T bit so it can come out again at the bottom
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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shortway:
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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vshortway:
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4 ; div1 r5,r0
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rotcl r4
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ret: rts
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mov r4,r0
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#endif
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