Iain Buclaw 433b6b12df d: Define IN_TARGET_CODE in all machine-specific D language files. ... This is to be consistent with the rest of the back-end. gcc/ChangeLog: * config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define. * config/arm/arm-d.c (IN_TARGET_CODE): Likewise. * config/i386/i386-d.c (IN_TARGET_CODE): Likewise. * config/mips/mips-d.c (IN_TARGET_CODE): Likewise. * config/pa/pa-d.c (IN_TARGET_CODE): Likewise. * config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise. * config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise. * config/s390/s390-d.c (IN_TARGET_CODE): Likewise. * config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.		2021-03-26 16:14:18 +01:00
..
arch-canonicalize	RISC-V: The 'multilib-generator' enhancement.	2021-01-19 11:44:47 +08:00
constraints.md	Update copyright years.	2021-01-04 10:26:59 +01:00
elf.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
freebsd.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
generic.md	Update copyright years.	2021-01-04 10:26:59 +01:00
linux.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
multilib-generator	RISC-V: The 'multilib-generator' enhancement.	2021-01-19 11:44:47 +08:00
peephole.md	Update copyright years.	2021-01-04 10:26:59 +01:00
pic.md	Update copyright years.	2021-01-04 10:26:59 +01:00
predicates.md	RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md	2021-03-23 17:32:41 +08:00
riscv-builtins.c	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-c.c	RISC-V: Implement new style of architecture extension test macros.	2021-01-08 11:14:02 +08:00
riscv-cores.def	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-d.c	d: Define IN_TARGET_CODE in all machine-specific D language files.	2021-03-26 16:14:18 +01:00
riscv-ftypes.def	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-modes.def	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-opts.h	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-passes.def	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-protos.h	Update copyright years.	2021-01-04 10:26:59 +01:00
riscv-shorten-memrefs.c	RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.	2021-02-13 12:33:44 -08:00
riscv-sr.c
riscv-subset.h	RISC-V: Implement new style of architecture extension test macros.	2021-01-08 11:14:02 +08:00
riscv.c	RISC-V: Fix riscv_subword() for big endian	2021-03-23 17:32:41 +08:00
riscv.h	RISC-V: Add riscv{32,64}be with big endian as default	2021-03-23 17:31:13 +08:00
riscv.md	RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md	2021-03-23 17:32:41 +08:00
riscv.opt	RISC-V: Support -mlittle-endian and -mbig-endian	2021-03-23 17:31:13 +08:00
rtems.h	Update copyright years.	2021-01-04 10:26:59 +01:00
sifive-7.md
sync.md	Update copyright years.	2021-01-04 10:26:59 +01:00
t-elf-multilib
t-linux
t-linux-multilib
t-riscv	RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h	2021-01-08 11:14:02 +08:00
t-rtems
t-withmultilib
t-withmultilib-generator