* config/sparc/sparc.c (vector_init_bshuffle): New function.
(vector_init_fpmerge): New function.
(sparc_expand_vector_init): Use them to improve non-const cases.
From-SVN: r180696
gcc/
* config/sparc/sparc.md (snedi_special): Only match when not VIS3.
(*snedi_zero): Likewise.
(*snedi_zero_trunc): Likewise.
(snedi_special_vis3): New expander.
(*snedi_zero_vis3): New insn.
(*snedi_zero_trunc_vis3): Likewise.
(*sltu_insn_vis3): Likewise.
(*sltu_insn_vis3_trunc): Likewise.
(addxc): Likewise.
(*addxc_trunc_sp64_vis3): Likewise.
* config/sparc/sparc.c (emit_scc_insn): When VIS3 use the
gen_snedi_special_vis3 expander, and try GTU/LTU addx based
sequences on DImode values.
gcc/testsuite/
* gcc.target/sparc/setcc-3.c: New test.
From-SVN: r180602
* config/sparc/sparc.c (emit_scc_insn): Force attempt of v9 sequences
if we're comparing DImode and comparison is other than EQ or NE.
From-SVN: r180558
gcc/
* config/sparc/sparc.c (emit_scc_insn): Do not try v9 sequences until
LEU/LTU/GEU/GTU is attempted.
* config/sparc/sparc.md (*neg_snesi_sign_extend): New 64-bit insn
and split.
(*neg_seqsi_sign_extend): Likewise.
(*sltu_extend_sp64, *neg_sltu_extend_sp64, *sgeu_extend_sp64,
*neg_sgeu_extend_sp64): New insns.
gcc/testsuite/
* gcc.target/sparc/setcc-1.c: New test.
* gcc.target/sparc/setcc-2.c: New test.
From-SVN: r180550
* config/sparc/sparc.c (sparc_option_override): Remove -mv8plus
cpu adjustment.
* config/sparc/linux64.h (CC1_SPEC): When defaulting to 64-bit,
append -mcpu=v9 when -mv8plus is given.
From-SVN: r180362
* config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): We can move
between float and non-float regs when VIS3.
* config/sparc/sparc.c (eligible_for_restore_insn): We can't
use a restore when the source is a float register.
(sparc_split_regreg_legitimate): When VIS3 allow moves between
float and integer regs.
(sparc_register_move_cost): Adjust to account for VIS3 moves.
(sparc_preferred_reload_class): On 32-bit with VIS3 when moving an
integer reg to a class containing EXTRA_FP_REGS, constrain to
FP_REGS.
(sparc_secondary_reload): On 32-bit with VIS3 when moving between
float and integer regs we sometimes need a FP_REGS class
intermediate move to satisfy the reload. When this happens
specify an extra cost of 2.
(*movsi_insn): Rename to have "_novis3" suffix and add !VIS3
guard.
(*movdi_insn_sp32_v9): Likewise.
(*movdi_insn_sp64): Likewise.
(*movsf_insn): Likewise.
(*movdf_insn_sp32_v9): Likewise.
(*movdf_insn_sp64): Likewise.
(*zero_extendsidi2_insn_sp64): Likewise.
(*sign_extendsidi2_insn): Likewise.
(*movsi_insn_vis3): New insn.
(*movdi_insn_sp32_v9_vis3): New insn.
(*movdi_insn_sp64_vis3): New insn.
(*movsf_insn_vis3): New insn.
(*movdf_insn_sp32_v9_vis3): New insn.
(*movdf_insn_sp64_vis3): New insn.
(*zero_extendsidi2_insn_sp64_vis3): New insn.
(*sign_extendsidi2_insn_vis3): New insn.
(TFmode reg/reg split): Make sure both REG operands are float.
(*mov<VM32:mode>_insn): Add "_novis3" suffix and !VIS3 guard. Remove
easy constant to integer reg alternatives.
(*mov<VM64:mode>_insn_sp64): Likewise.
(*mov<VM64:mode>_insn_sp32_novis3): Likewise.
(*mov<VM32:mode>_insn_vis3): New insn.
(*mov<VM64:mode>_insn_sp64_vis3): New insn.
(*mov<VM64:mode>_insn_sp32_vis3): New insn.
(VM64 reg<-->reg split): New spliiter for 32-bit.
From-SVN: r180360
* config/sparc/predicates.md (input_operand): Disallow vector
constants other than 0 and -1.
* config/sparc/sparc.c (sparc_preferred_reload_class): Return
NO_REGS for vector constants other than 0 and -1.
From-SVN: r180351
* config/sparc/sol2.h: Protect -m{cpu,tune}=native handling
with a more complete cpp test.
* config/sparc/linux64.h: Likewise.
* config/sparc/linux.h: Likewise.
* config/sparc/sparc.opt (sparc_debug): New target variable.
(mdebug): New target option.
* config/sparc/sparc.h (MASK_DEBUG_OPTIONS, MASK_DEBUG_ALL,
TARGET_DEBUG_OPTIONS): New defines.
* config/sparc/sparc.c (debug_target_flag_bits,
debug_target_flags): New functions.
(sparc_option_override): Add name strings back to cpu_table[].
Parse -mdebug string. When TARGET_DEBUG_OPTIONS is true, print
out the target flags before and after override processing as well
as the selected cpu. If MASK_V8PLUS, make sure that the selected
cpu is at least v9.
From-SVN: r180021
* config/sparc/sparc.md (UNSPEC_FPMERGE): Delete.
(UNSPEC_MUL16AU, UNSPEC_MUL8, UNSPEC_MUL8SU, UNSPEC_MULDSU): New
unspecs.
(fpmerge_vis): Remove inaccurate comment, represent using vec_select
of a vec_concat.
(vec_interleave_lowv8qi, vec_interleave_highv8qi): New insns.
(fmul8x16_vis, fmul8x16au_vis, fmul8sux16_vis, fmuld8sux16_vis):
Reimplement as unspecs and remove inaccurate comments.
(vis3_shift_patname): New code attr.
(<vis3_shift_insn><vbits>_vis): Rename to "v<vis3_shift_patname><mode>3".
(vis3_addsub_ss_patname): New code attr.
(<vis3_addsub_ss_insn><vbits>_vis): Rename to
"<vis3_addsub_ss_patname><mode>3".
* config/sparc/sparc.c (sparc_vis_init_builtins): Update to
accommodate pattern name changes.
From-SVN: r179943
gcc/
* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
to zero when assembler lacks support for such instructions.
* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
and MASK_FMAF in defaults when assembler lacks necessary support.
gcc/testsuite/
* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
'-mvis3' instead of 'mcpu=niagara3' in options.
* gcc.target/sparc/fhalve.c: Likewise.
* gcc.target/sparc/fnegop.c: Likewise.
* gcc.target/sparc/fpadds.c: Likewise.
* gcc.target/sparc/fshift.c: Likewise.
* gcc.target/sparc/fucmp.c: Likewise.
* gcc.target/sparc/lzd.c: Likewise.
* gcc.target/sparc/vis3misc.c: Likewise.
* gcc.target/sparc/xmul.c: Likewise.
From-SVN: r179875
gcc/
* config/sparc/sparc.opt (VIS3): New option.
* doc/invoke.texi: Document it.
* config/sparc/sparc.h: Force TARGET_VIS3 to zero if assembler is
not capable of such instructions.
* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__
to 0x300 when TARGET_VIS3.
* config/sparc/sparc-modes.def: Create 16-byte vector modes.
* config/sparc/sparc.md (UNSPEC_CMASK8, UNSPEC_CMASK16, UNSPEC_CMASK32,
UNSPEC_FCHKSM16, UNSPEC_PDISTN, UNSPC_FUCMP): New unspecs.
(V64N8, VASS): New mode iterators.
(vis3_shift, vis3_addsub_ss): New code iterators.
(vbits, vconstr): New mode attributes.
(vis3_shift_insn, vis3_addsub_ss_insn): New code attributes.
(cmask8<P:mode>_vis, cmask16<P:mode>_vis, cmask32<P:mode>_vis,
fchksm16_vis, <vis3_shift_insn><vbits>_vis, pdistn<mode>_vis,
fmean16_vis, fpadd64_vis, fpsub64_vis, <vis3_addsub_ss_insn><vbits>_vis,
fucmp<code>8<P:mode>_vis): New VIS 3.0 instruction patterns.
* config/sparc/sparc.c (sparc_option_override): Set MASK_VIS3 by
default when targetting capable cpus. TARGET_VIS3 implies
TARGET_VIS2 and TARGET_VIS, and clear them when TARGET_FPU is
disabled.
(sparc_vis_init_builtins): Emit new VIS 3.0 builtins.
(sparc_fold_builtin): Do not eliminate cmask{8,16,32} when result
is ignored.
* config/sparc/visintrin.h (__vis_cmask8, __vis_cmask16,
__vis_cmask32, __vis_fchksm16, __vis_fsll16, __vis_fslas16,
__vis_fsrl16, __vis_fsra16, __vis_fsll32, __vis_fslas32,
__vis_fsrl32, __vis_fsra32, __vis_pdistn, __vis_fmean16,
__vis_fpadd64, __vis_fpsub64, __vis_fpadds16, __vis_fpadds16s,
__vis_fpsubs16, __vis_fpsubs16s, __vis_fpadds32, __vis_fpadds32s,
__vis_fpsubs32, __vis_fpsubs32s, __vis_fucmple8, __vis_fucmpne8,
__vis_fucmpgt8, __vis_fucmpeq8): New VIS 3.0 interfaces.
* doc/extend.texi: Document new VIS 3.0 builtins.
gcc/testsuite/
* gcc.target/sparc/cmask.c: New test.
* gcc.target/sparc/fpadds.c: New test.
* gcc.target/sparc/fshift.c: New test.
* gcc.target/sparc/fucmp.c: New test.
* gcc.target/sparc/vis3misc.c: New test.
From-SVN: r179421
gcc/
* config/sparc/sparc.opt (VIS2): New option.
* doc/invoke.texi: Document it.
* config/sparc/sparc.md (UNSPEC_EDGE8N, UNSPEC_EDGE8LN,
UNSPEC_EDGE16N, UNSPEC_EDGE16LN, UNSPEC_EDGE32N,
UNSPEC_EDGE32LN, UNSPEC_BSHUFFLE): New unspecs.
(define_attr type): New insn type 'edgen'.
(bmask<P:mode>_vis, bshuffle<V64I:mode>_vis, edge8n<P:mode>_vis,
edge8ln<P:mode>_vis, edge16n<P:mode>_vis, edge16ln<P:mode>_vis,
edge32n<P:mode>_vis, edge32ln<P:mode>_vis): New insn VIS 2.0
patterns.
* niagara.md: Handle edgen.
* niagara2.md: Likewise.
* ultra1_2.md: Likewise.
* ultra3.md: Likewise.
* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__
to 0x200 when TARGET_VIS2.
* config/sparc/sparc.c (sparc_option_override): Set MASK_VIS2 by
default when targetting capable cpus. TARGET_VIS2 implies
TARGET_VIS, clear and it when TARGET_FPU is disabled.
(sparc_vis_init_builtins): Emit new VIS 2.0 builtins.
(sparc_expand_builtin): Fix predicate indexing when builtin returns
void.
(sparc_fold_builtin): Do not eliminate bmask when result is ignored.
* config/sparc/visintrin.h (__vis_bmask, __vis_bshuffledi,
__vis_bshufflev2si, __vis_bshufflev4hi, __vis_bshufflev8qi,
__vis_edge8n, __vis_edge8ln, __vis_edge16n, __vis_edge16ln,
__vis_edge32n, __vis_edge32ln): New VIS 2.0 interfaces.
* doc/extend.texi: Document new VIS 2.0 builtins.
gcc/testsuite/
* gcc.target/sparc/bmaskbshuf.c: New test.
* gcc.target/sparc/edgen.c: New test.
From-SVN: r179376
Improve code generation for edge and pixel-compare, specifically avoid
sign and zero extensions on 64-bit and allow such instructions to be
placed in delay slots.
gcc/
* config/sparc/sparc.md (edge{8,16,32}{,l}): Return Pmode.
(fcmp{le,ne,gt,eq}{16,32}): Likewise.
* config/sparc/visintrin.h: Update edge and pixel-compare
intrinsics to return 'long' instead of 'int'.
* doc/extend.texi: Update documentation to match.
* config/sparc/sparc.c (eligible_for_return_delay): When leaf or
flat, allow any instruction. Otherwise, when V9 allow parallels
which consist only of sets to registers outside of %o0 to %o5.
(sparc_vis_init_builtins): Update VIS builtin types for edge
and pixel-compare.
gcc/testsuite/
* gcc.target/sparc/edge.c: Update for new return types.
* gcc.target/sparc/fcmp.c: Likewise.
From-SVN: r179227
gcc/
* config/sparc/sparc.c (sparc_conditional_register_usage): When VIS
is enabled, mark %gsr as global.
* config/sparc/sparc.md (UNSPEC_WRGSR): Delete.
(wrgsr_vis, *wrgsr_sp64, wrgsr_v8plus): Don't wrap in an unspec.
gcc/testsuite/
* gcc.target/sparc/wrgsr.c: New test.
From-SVN: r179214
* configure.ac: Add feature check to make sure the assembler
supports the FMAF, HPC, and VIS 3.0 instructions found on
Niagara-3 and later cpus.
* configure: Rebuild.
* config.in: Likewise.
* config/sparc/sparc.opt: New option '-mfmaf'.
* config/sparc/sparc.md: Add float fused multiply-add patterns.
* config/sparc/sparc.h (AS_NIAGARA3_FLAG): New macro.
(ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Use it, as needed.
* config/sparc/sol2.h (ASM_CPU32_DEFAULT_SPEC,
ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Likewise.
* config/sparc/sparc.c (sparc_option_override): Turn MASK_FMAF on
by default for Niagara-3 and later. Turn it off if TARGET_FPU is
disabled.
(sparc_rtx_costs): Handle 'FMA'.
* doc/invoke.texi: Document -mfmaf.
From-SVN: r179174
* config/sparc/constraints.md (C, P, Z): New constraints for
const_doube, const_int, and const_vector "all ones" values.
Make unused constraint letters comment match reality.
* config/sparc/predicates.md (const_all_ones_operand,
register_or_zero_or_all_ones_operand): New predicates.
* config/sparc/sparc.c (sparc_expand_move): Allow all ones
as well as zero constants when VIS.
(sparc_legitimate_constant_p): Likewise.
* config/sparc/sparc.md (movsi_insn): Add fones alternative.
(movsf_insn): Likewise
(movdi_insn_sp64): Add fone alternative.
(movdf_insn_sp32_v9): Likewise.
(movdf_insn_sp64): Likewise.
From-SVN: r179173
* config/sparc/sparc.h (FIRST_PSEUDO_REGISTER): Bump to 103.
(SPARC_GSR_REG): Define.
(FIXED_REGISTERS): Mark GSR as fixed.
(CALL_USED_REGISTERS): Mark GSR as call used.
(HARD_REGNO_NREGS): GSR is always 1 register.
(REG_CLASS_CONTENTS): Add GSR to ALL_REGS.
(REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER): Add GSR to the end.
(REGISTER_NAMES): Add "%gsr".
* config/sparc/sparc.md (UNSPEC_ALIGNADDR, UNSPEC_ALIGNADDRL):
Delete.
(UNSPEC_WRGSR): New unspec.
(GSR_REG): New constant.
(type): Add new insn type 'gsr'.
(fpack16_vis, fpackfix_vis, fpack32_vis,
faligndata<V64I:MODE>_vis)): Add use of GSR_REG.
(wrgsr_vis, *wrgsr_sp64, wrgsr_v8plus, rdgsr_vis, *rdgsr_sp64,
rdgsr_v8plus): New expanders and insns.
(alignaddr<P:mode>_vis, alignaddrl<P:mode>_vis): Reimplement
using patterns which show that this is a plus in addition to a
modification of GSR_REG, instead of an unspec.
* config/sparc/ultra1_2.md: Handle 'gsr'.
* config/sparc/ultra3.md: Likewise.
* config/sparc/niagara.md: Likewise.
* config/sparc/niagara2.md: Likewise.
* config/sparc/sparc.c (leaf_reg_remap, sparc_leaf_regs): Fill out
end of table.
(sparc_option_override): Make -mvis imply -mv8plus.
(hard_32bit_mode_classes, hard_64bit_mode_classes): Add entries
for %gsr.
(sparc_vis_init_builtins): Build __builtin_vis_write_gsr and
__builtin_vis_read_gsr.
(sparc_expand_buildin): Handle builtins that take one argument and
return void.
(sparc_fold_builtin): Never fold writes to %gsr.
* config/sparc/visintrin.h (__vis_write_gsr, __vis_read_gsr): New.
* doc/extend.texi: Document new VIS intrinsics.
From-SVN: r179159
* config/sparc/sparc.c (def_builtin): Change from macro into function.
(def_builtin_const): New.
(sparc_vis_init_builtins): Use def_builtin_const for all VIS builtins
other than alignaddr and falignaddr.
From-SVN: r179035
* config/sparc/sparc.md (UNSPEC_ALIGNADDRL): New unspec.
(aligneddrl<P:mode>_vis): New pattern.
(edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis,
edge32l_vis): Adjust to take Pmode arguments, and return SImode.
* config/sparc/sparc.c (sparc_vis_init_builtins): Handle new
alignaddrl insn, and adjust edge operations for updated types.
* config/sparc/visintrin.h: Likewise.
* doc/extend.texi: Make typing in VIS documentation match reality.
From-SVN: r179012
* gcc/config/sparc/sparc.c (niagara2_costs): Adjust integer
divide costs.
(niagara3_costs): New.
(sparc_option_override): Use it.
* gcc/config/sparc/niagara2.md: Adjust with more accurate
Niagara-3 reservations.
From-SVN: r178938
