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re PR middle-end/18041 (OR of two single-bit bitfields is inefficient)

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2018-11-06  Richard Biener  <rguenther@suse.de>

	PR middle-end/18041
	* simplify-rtx.c (simplify_binary_operation_1): Add pattern
	matching bitfield insertion.

	* gcc.target/i386/pr18041-1.c: New testcase.
	* gcc.target/i386/pr18041-2.c: Likewise.

From-SVN: r265829
This commit is contained in:
Richard Biener 2018-11-06 08:09:03 +00:00 committed by Richard Biener
parent 91c03124fc
commit ffe5a586cc
5 changed files with 71 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2018-11-06 Richard Biener <rguenther@suse.de>
PR middle-end/18041
* simplify-rtx.c (simplify_binary_operation_1): Add pattern
matching bitfield insertion.
2018-11-06 Alexandre Oliva <aoliva@redhat.com>
* auto-inc-dec.c: Include valtrack.h. Improve comments.

32
gcc/simplify-rtx.c
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@ -2857,6 +2857,38 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
XEXP (op0, 1));
}
/* The following happens with bitfield merging.
(X & C) | ((X | Y) & ~C) -> X | (Y & ~C) */
if (GET_CODE (op0) == AND
&& GET_CODE (op1) == AND
&& CONST_INT_P (XEXP (op0, 1))
&& CONST_INT_P (XEXP (op1, 1))
&& (INTVAL (XEXP (op0, 1))
== ~INTVAL (XEXP (op1, 1))))
{
/* The IOR may be on both sides. */
rtx top0 = NULL_RTX, top1 = NULL_RTX;
if (GET_CODE (XEXP (op1, 0)) == IOR)
top0 = op0, top1 = op1;
else if (GET_CODE (XEXP (op0, 0)) == IOR)
top0 = op1, top1 = op0;
if (top0 && top1)
{
/* X may be on either side of the inner IOR. */
rtx tem = NULL_RTX;
if (rtx_equal_p (XEXP (top0, 0),
XEXP (XEXP (top1, 0), 0)))
tem = XEXP (XEXP (top1, 0), 1);
else if (rtx_equal_p (XEXP (top0, 0),
XEXP (XEXP (top1, 0), 1)))
tem = XEXP (XEXP (top1, 0), 0);
if (tem)
return simplify_gen_binary (IOR, mode, XEXP (top0, 0),
simplify_gen_binary
(AND, mode, tem, XEXP (top1, 1)));
}
}
tem = simplify_byte_swapping_operation (code, mode, op0, op1);
if (tem)
return tem;

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2018-11-06 Richard Biener <rguenther@suse.de>
PR middle-end/18041
* gcc.target/i386/pr18041-1.c: New testcase.
* gcc.target/i386/pr18041-2.c: Likewise.
2018-11-06 Wei Xiao <wei3.xiao@intel.com>
* gcc.target/i386/avx-1.c: Update tests for VFIXUPIMM* intrinsics.

13
gcc/testsuite/gcc.target/i386/pr18041-1.c Normal file
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@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
struct B { unsigned bit0 : 1; unsigned bit1 : 1; };
void
foo (struct B *b)
{
b->bit0 = b->bit0 | b->bit1;
}
/* { dg-final { scan-assembler-times "and" 1 } } */
/* { dg-final { scan-assembler-times "or" 1 } } */

14
gcc/testsuite/gcc.target/i386/pr18041-2.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
struct B { unsigned bit0 : 1; unsigned bit1 : 1; };
void
bar (struct B *b, int x)
{
b->bit0 |= x;
}
/* This fails to combine in 32bit mode but not for x32. */
/* { dg-final { scan-assembler-times "and" 1 { xfail { { ! x32 } && ilp32 } } } } */
/* { dg-final { scan-assembler-times "or" 1 { xfail { { ! x32 } && ilp32 } } } } */