(storehi_bigend): New expansion pattern.
(storeinthi): Rework to generate better code, add big-endian support. (movhi): Add support for processors running in big-endian mode. (movhi_bigend): New expansion pattern. (matcher for movhi): Remove incorrect alternative for storing HImode to memory. Only match when little endian. (matcher for big-endian movhi): New pattern. (matchers/peepholes for extended pre/post increment HImode loads): Only match when little-endian. (matcher for operating on adjacent memory locations): Load operation into arith operands. (peepholes for extended pre-increment byte loads): New patterns. From-SVN: r7448
This commit is contained in:
Richard Earnshaw
parent
9c8728721e
commit
fe241a29e3
@ -1983,30 +1983,69 @@
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}
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")
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;; Subroutine to store a half word integer constant into memory.
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;; Operand 0 is the constant
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;; Operand 1 is the destination address in a register (SImode)
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(define_expand "storeinthi"
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[;; store the low byte
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(set (mem:QI (match_operand:SI 1 "" "")) (match_operand 0 "" ""))
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;; store the high byte
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(set (mem:QI (match_dup 3)) (match_dup 2))]
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(define_expand "storehi_bigend"
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[(set (mem:QI (match_dup 4)) (match_dup 3))
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(set (match_dup 2)
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(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
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(set (mem:QI (match_operand 1 "" ""))
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(subreg:QI (match_dup 2) 0))]
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""
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"
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{
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int value = INTVAL (operands[0]);
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enum rtx_code code = GET_CODE (operands[1]);
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if ((code == PLUS || code == MINUS)
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&& (GET_CODE (XEXP (operands[1], 1)) == REG
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|| GET_CODE (XEXP (operands[1], 0)) != REG))
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operands[1] = force_reg (SImode, operands[1]);
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operands[1] = force_reg (SImode, operands[1]);
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operands[0] = force_reg (QImode, gen_rtx (CONST_INT, VOIDmode, value & 255));
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operands[2] = force_reg (QImode,
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gen_rtx (CONST_INT, VOIDmode,(value>>8) & 255));
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operands[3] = plus_constant (operands[1], 1);
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operands[4] = plus_constant (operands[1], 1);
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operands[3] = gen_lowpart (QImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[2] = gen_reg_rtx (SImode);
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}
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")
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;; Subroutine to store a half word integer constant into memory.
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(define_expand "storeinthi"
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[(set (mem:QI (match_operand:SI 0 "" ""))
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(subreg:QI (match_operand 1 "" "") 0))
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(set (mem:QI (match_dup 3)) (subreg:QI (match_dup 2) 0))]
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""
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"
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{
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HOST_WIDE_INT value = INTVAL (operands[1]);
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enum rtx_code code = GET_CODE (operands[0]);
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if ((code == PLUS || code == MINUS)
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&& (GET_CODE (XEXP (operands[0], 1)) == REG
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|| GET_CODE (XEXP (operands[0], 0)) != REG))
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operands[0] = force_reg (SImode, operands[0]);
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operands[1] = gen_reg_rtx (SImode);
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if (BYTES_BIG_ENDIAN)
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{
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emit_insn (gen_movsi (operands[1], GEN_INT ((value >> 8) & 255)));
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if ((value & 255) == ((value >> 8) & 255))
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operands[2] = operands[1];
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else
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{
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operands[2] = gen_reg_rtx (SImode);
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emit_insn (gen_movsi (operands[2], GEN_INT (value & 255)));
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}
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}
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else
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{
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emit_insn (gen_movsi (operands[1], GEN_INT (value & 255)));
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if ((value & 255) == ((value >> 8) & 255))
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operands[2] = operands[1];
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else
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{
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operands[2] = gen_reg_rtx (SImode);
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emit_insn (gen_movsi (operands[2], GEN_INT ((value >> 8) & 255)));
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}
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}
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operands[3] = plus_constant (operands[0], 1);
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}
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")
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@ -2018,74 +2057,105 @@
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{
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rtx insn;
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if (reload_in_progress || reload_completed)
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insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]);
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else
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if (! (reload_in_progress || reload_completed))
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{
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if (GET_CODE (operands[0]) == MEM)
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{
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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insn = gen_storeinthi (operands[1], XEXP (operands[0],0));
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}
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emit_insn (gen_storeinthi (XEXP (operands[0], 0), operands[1]));
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else
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{
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if (GET_CODE (operands[1]) == MEM)
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operands[1] = force_reg (HImode, operands[1]);
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insn = gen_storehi (operands[1], XEXP (operands[0], 0));
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_storehi_bigend (operands[1],
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XEXP (operands[0], 0)));
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else
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emit_insn (gen_storehi (operands[1], XEXP (operands[0], 0)));
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}
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DONE;
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}
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else if (GET_CODE (operands[1]) == CONST_INT
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&& !(const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1]))))
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/* Sign extend a constant, and keep it in an SImode reg. */
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else if (GET_CODE (operands[1]) == CONST_INT)
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{
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rtx reg, reg2;
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rtx reg = gen_reg_rtx (SImode);
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HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
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/* no need to be clever, this will always take two insns.
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The top sixteen bits should be all zeros or all ones. */
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if (INTVAL (operands[1]) < 0)
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/* If the constant is already valid, leave it alone. */
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if (! const_ok_for_arm (val))
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{
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emit_insn (gen_movsi (reg = gen_reg_rtx (SImode),
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GEN_INT (INTVAL (operands[1])
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| ~(0x0ff00))));
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emit_insn (gen_addsi3 (reg2 = gen_reg_rtx (SImode), reg,
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GEN_INT (-((~INTVAL (operands[1]))
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& 0xff))));
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/* If setting all the top bits will make the constant
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loadable in a single instruction, then set them.
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Otherwise, sign extend the number. */
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if (const_ok_for_arm (~ (val | ~0xffff)))
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val |= ~0xffff;
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else if (val & 0x8000)
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val |= ~0xffff;
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}
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else
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{
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emit_insn (gen_movsi (reg = gen_reg_rtx (SImode),
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GEN_INT (INTVAL (operands[1]) & 0xff00)));
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emit_insn (gen_addsi3 (reg2 = gen_reg_rtx (SImode), reg,
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GEN_INT (INTVAL (operands[1]) & 0x00ff)));
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}
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insn = gen_rtx (SET, HImode, operands[0],
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gen_rtx (SUBREG, HImode, reg2, 0));
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emit_insn (gen_movsi (reg, GEN_INT (val)));
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operands[1] = gen_rtx (SUBREG, HImode, reg, 0);
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}
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else if (BYTES_BIG_ENDIAN && GET_CODE (operands[1]) == MEM)
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{
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emit_insn (gen_movhi_bigend (operands[0], operands[1]));
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DONE;
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}
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else
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insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]);
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}
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}
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")
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emit_insn (insn);
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DONE;
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}")
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(define_expand "movhi_bigend"
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[(set (match_dup 2)
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(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "") 0)
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(const_int 16)))
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(set (match_dup 3)
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(ashiftrt:SI (match_dup 2) (const_int 16)))
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(set (match_operand:HI 0 "s_register_operand" "")
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(subreg:HI (match_dup 3) 0))]
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""
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"
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operands[2] = gen_reg_rtx (SImode);
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operands[3] = gen_reg_rtx (SImode);
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")
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;; Pattern to recognise insn generated default case above
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(define_insn ""
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[(set (match_operand:HI 0 "general_operand" "=r,r,r,m")
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(match_operand:HI 1 "general_operand" "rI,K,m,r"))]
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"(register_operand (operands[0], HImode)
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&& (GET_CODE (operands[1]) != CONST_INT
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|| const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1]))))
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|| register_operand (operands[1], HImode)"
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[(set (match_operand:HI 0 "general_operand" "=r,r,r")
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(match_operand:HI 1 "general_operand" "rI,K,m"))]
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"(! BYTES_BIG_ENDIAN)
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&& (GET_CODE (operands[1]) != CONST_INT
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|| const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1])))"
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"@
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mov%?\\t%0, %1\\t%@ movhi
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mvn%?\\t%0, #%B1\\t%@ movhi
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ldr%?\\t%0, %1\\t%@ movhi
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bogus code str%?\\t%1, %0\\t%@ movhi"
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[(set_attr "type" "*,*,load,store1")])
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ldr%?\\t%0, %1\\t%@ movhi"
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[(set_attr "type" "*,*,load")])
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(define_insn ""
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[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
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(match_operand:HI 1 "general_operand" "rI,K,m"))]
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"BYTES_BIG_ENDIAN
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&& (GET_CODE (operands[1]) != CONST_INT
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|| const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1])))"
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"@
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mov%?\\t%0, %1\\t%@ movhi
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mvn%?\\t%0, #%B1\\t%@ movhi
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ldr%?\\t%0, %1\\t%@ movhi_bigend\;mov%?\\t%0, %0, asr #16"
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[(set_attr "type" "*,*,load")
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(set_attr "length" "4,4,8")])
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(define_insn ""
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
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(const_int 16)))]
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"BYTES_BIG_ENDIAN"
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"ldr%?\\t%0, %1\\t%@ movhi_bigend"
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[(set_attr "type" "load")])
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(define_expand "reload_outhi"
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[(parallel [(match_operand:HI 0 "reload_memory_operand" "=o")
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@ -2106,10 +2176,11 @@
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if (!(reload_in_progress || reload_completed))
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{
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rtx reg;
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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emit_insn (gen_movsi (reg = gen_reg_rtx (SImode), operands[1]));
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rtx reg = gen_reg_rtx (SImode);
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emit_insn (gen_movsi (reg, operands[1]));
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operands[1] = gen_rtx (SUBREG, QImode, reg, 0);
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}
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}
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@ -4335,7 +4406,7 @@
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"*
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{
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rtx ldm[3];
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rtx arith[3];
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rtx arith[4];
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int val1 = 0, val2 = 0;
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if (REGNO (operands[0]) > REGNO (operands[4]))
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@ -4353,6 +4424,7 @@
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if (GET_CODE (XEXP (operands[3], 0)) != REG)
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val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1));
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arith[0] = operands[0];
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arith[3] = operands[1];
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if (val1 < val2)
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{
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arith[1] = ldm[1];
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@ -4391,7 +4463,7 @@
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else
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output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm);
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}
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output_asm_insn (\"%I1%?\\t%0, %1, %2\", arith);
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output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith);
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return \"\";
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}
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"
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@ -4546,7 +4618,8 @@
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(match_operand:SI 2 "index_operand" "rJ"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"REGNO (operands[0]) != FRAME_POINTER_REGNUM
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"(! BYTES_BIG_ENDIAN)
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& (GET_CODE (operands[2]) != REG
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|| REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
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@ -4559,7 +4632,8 @@
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(match_operand:SI 2 "s_register_operand" "r"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"REGNO (operands[0]) != FRAME_POINTER_REGNUM
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"(!BYTES_BIG_ENDIAN)
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& (GET_CODE (operands[2]) != REG
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|| REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
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@ -4695,7 +4769,8 @@
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"REGNO (operands[0]) != FRAME_POINTER_REGNUM
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"(! BYTES_BIG_ENDIAN)
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
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"ldr%?\\t%5, [%0, %3, %S2]!\\t%@ loadhi"
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@ -4710,7 +4785,8 @@
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"REGNO (operands[0]) != FRAME_POINTER_REGNUM
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"(! BYTES_BIG_ENDIAN)
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
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"ldr%?\\t%5, [%0, -%3, %S2]!\\t%@ loadhi"
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@ -4730,7 +4806,7 @@
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
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""
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"strb\\t%2, [%0], %1")
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"str%?b\\t%2, [%0], %1")
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(define_peephole
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[(set (match_operand:QI 0 "s_register_operand" "=r")
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@ -4755,7 +4831,8 @@
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(mem:HI (match_operand:SI 1 "s_register_operand" "+r")))
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(set (match_dup 1)
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(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
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"REGNO(operands[0]) != REGNO(operands[1])
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"(! BYTES_BIG_ENDIAN)
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&& REGNO(operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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"ldr%?\\t%0, [%1], %2\\t%@ loadhi")
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@ -4770,6 +4847,25 @@
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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"ldr%?\\t%0, [%1], %2")
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(define_peephole
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[(set (mem:QI (plus:SI (match_operand:SI 0 "s_register_operand" "+r")
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(match_operand:SI 1 "index_operand" "rJ")))
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(match_operand:QI 2 "s_register_operand" "r"))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
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""
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"str%?b\\t%2, [%0, %1]!")
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(define_peephole
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[(set (mem:QI (plus:SI (match_operator:SI 4 "shift_operator"
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[(match_operand:SI 0 "s_register_operand" "r")
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(match_operand 1 "const_int_operand" "n")])
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(match_operand:SI 2 "s_register_operand" "+r")))
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(match_operand:QI 3 "s_register_operand" "r"))
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(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
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(match_dup 2)))]
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""
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"str%?b\\t%3, [%2, %0, %S4]!")
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; This pattern is never tried by combine, so do it as a peephole
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(define_peephole
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