(logical patterns): Tune to give better code for immediate values.
From-SVN: r7476
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@ -102,12 +102,13 @@
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andn %0,%1,%C2")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI"))
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(match_operand:SI 2 "gpc_reg_operand" "r")))]
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
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""
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"andn %0,%2,%1")
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"@
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andn %0,%2,%1
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nor %0,%1,%C2")
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;; CALLI
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;;
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@ -1196,7 +1197,7 @@
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
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(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
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(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
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""
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"nand %0,%1,%2")
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@ -1204,24 +1205,18 @@
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
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(match_operand:SI 2 "const_int_operand" "K")))]
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"((unsigned) ~ INTVAL (operands[2])) < 256"
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; Match TARGET_29050 in "orn" pattern for slightly better reload.
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"! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
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"nand %0,%1,%C2")
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;; NOR
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
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(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
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(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
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""
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"nor %0,%1,%2")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
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(match_operand:SI 2 "const_int_operand" "K")))]
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"((unsigned) ~ INTVAL (operands[2])) < 256"
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"nor %0,%1,%C2")
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(define_insn "one_cmplsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
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@ -1246,12 +1241,21 @@
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
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(match_operand:SI 2 "srcb_operand" "rI,K")))]
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(match_operand:SI 2 "and_operand" "rI,K")))]
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"TARGET_29050"
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"@
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or %0,%1,%2
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orn %0,%1,%C2")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
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"TARGET_29050"
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"@
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orn %0,%2,%1
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nand %0,%1,%C2")
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;; SLL (also used by move insn)
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(define_insn "nop"
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@ -1512,17 +1516,20 @@
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
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(match_operand:SI 2 "srcb_operand" "rI"))))]
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(match_operand:SI 2 "gpc_reg_operand" "r"))))]
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""
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"xnor %0,%1,%2")
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;; XOR
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
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(match_operand:SI 2 "srcb_operand" "rI")))]
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
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(match_operand:SI 2 "and_operand" "rI,K")))]
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""
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"xor %0,%1,%2")
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"@
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xor %0,%1,%2
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xnor %0,%1,%C2")
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;; Can use XOR to negate floating-point values, but we are better off not doing
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;; it that way on the 29050 so it can combine with the fmac insns.
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