(movsi matcher): Add nop for moving special register to itself for !TARGET_POWER.
(movsi matcher): Add nop for moving special register to itself for !TARGET_POWER. (movhi and movqi matcher): Likewise and add mtjmpr attribute. Separate MQ from CTR and LR target registers for TARGET_POWER. From-SVN: r7736
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@ -3574,8 +3574,8 @@
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[(set_attr "type" "*,load,*,*,*,*,*,mtjmpr,*")])
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
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(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h,*h")
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(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,0"))]
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"! TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
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|| gpc_reg_operand (operands[1], SImode))"
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"@
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@ -3585,8 +3585,9 @@
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li %0,%1
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lis %0,%u1
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mf%1 %0
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mt%0 %1"
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr")])
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
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;; Split a load of a large constant into the appropriate two-insn
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;; sequence.
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@ -3637,8 +3638,8 @@
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}")
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(define_insn ""
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
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(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
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(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
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"TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
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|| gpc_reg_operand (operands[1], HImode))"
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"@
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@ -3648,12 +3649,13 @@
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{cal %0,%w1(0)|li %0,%w1}
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mf%1 %0
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mt%0 %1
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,*,*")])
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
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(define_insn ""
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
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(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
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(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
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"! TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
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|| gpc_reg_operand (operands[1], HImode))"
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"@
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@ -3662,8 +3664,9 @@
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sth%U0%X0 %1,%0
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li %0,%w1
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mf%1 %0
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mt%0 %1"
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[(set_attr "type" "*,load,*,*,*,*")])
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,mtjmpr,*")])
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
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@ -3685,8 +3688,8 @@
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}")
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(define_insn ""
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
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(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
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(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
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"TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
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|| gpc_reg_operand (operands[1], QImode))"
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"@
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@ -3696,12 +3699,13 @@
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{cal %0,%1(0)|li %0,%1}
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mf%1 %0
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mt%0 %1
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,*,*")])
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
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(define_insn ""
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
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(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
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(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
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"! TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
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|| gpc_reg_operand (operands[1], QImode))"
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"@
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@ -3710,8 +3714,9 @@
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stb%U0%X0 %1,%0
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li %0,%1
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mf%1 %0
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mt%0 %1"
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[(set_attr "type" "*,load,*,*,*,*")])
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,mtjmpr,*")])
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;; Here is how to move condition codes around. When we store CC data in
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;; an integer register or memory, we store just the high-order 4 bits.
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