rs6000: Enable 32bit variable vec_insert [PR99718]
32bit and P7 VSX could also benefit a lot from the variable vec_insert implementation with shift/insert/shift back method. 2011-03-29 Xionghu Luo <luoxhu@linux.ibm.com> PR target/99718 * config/rs6000/altivec.md (altivec_lvsl_reg): Change to ... (altivec_lvsl_reg_<mode>): ... this. (altivec_lvsr_reg): Change to ... (altivec_lvsr_reg_<mode>): ... this. * config/rs6000/predicates.md (vec_set_index_operand): New. * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Enable 32bit variable vec_insert for all TARGET_VSX. * config/rs6000/rs6000.c (rs6000_expand_vector_set_var_p9): Enable 32bit variable vec_insert for p9 and above. (rs6000_expand_vector_set_var_p8): Rename to ... (rs6000_expand_vector_set_var_p7): ... this. (rs6000_expand_vector_set): Use TARGET_VSX and adjust assert position. * config/rs6000/vector.md (vec_set<mode>): Use vec_set_index_operand. * config/rs6000/vsx.md (xl_len_r): Use gen_altivec_lvsl_reg_di and gen_altivec_lvsr_reg_di. gcc/testsuite/ PR target/99718 * gcc.target/powerpc/fold-vec-insert-char-p8.c: Update instruction counts. * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-double.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. * gcc.target/powerpc/pr79251.p8.c: Likewise. * gcc.target/powerpc/pr79251.p9.c: Likewise. * gcc.target/powerpc/vsx-builtin-7.c: Likewise. * gcc.target/powerpc/pr79251-run.p7.c: New test. * gcc.target/powerpc/pr79251.p7.c: New test.
This commit is contained in:
luoxhu@cn.ibm.com
Segher Boessenkool
parent
5463cee277
commit
f64b91568f
@ -2771,10 +2771,10 @@
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DONE;
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})
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(define_insn "altivec_lvsl_reg"
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(define_insn "altivec_lvsl_reg_<mode>"
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[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
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(unspec:V16QI
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[(match_operand:DI 1 "gpc_reg_operand" "b")]
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[(match_operand:GPR 1 "gpc_reg_operand" "b")]
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UNSPEC_LVSL_REG))]
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"TARGET_ALTIVEC"
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"lvsl %0,0,%1"
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@ -2809,10 +2809,10 @@
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DONE;
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})
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(define_insn "altivec_lvsr_reg"
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(define_insn "altivec_lvsr_reg_<mode>"
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[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
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(unspec:V16QI
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[(match_operand:DI 1 "gpc_reg_operand" "b")]
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[(match_operand:GPR 1 "gpc_reg_operand" "b")]
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UNSPEC_LVSR_REG))]
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"TARGET_ALTIVEC"
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"lvsr %0,0,%1"
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@ -1940,3 +1940,9 @@
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return !indexed_address (addr, mode);
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})
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;; Return 1 if this operand is valid as the index for vec_set.
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(define_predicate "vec_set_index_operand"
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(if_then_else (match_test "TARGET_VSX")
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(match_operand 0 "reg_or_cint_operand")
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(match_operand 0 "const_int_operand")))
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@ -1602,7 +1602,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
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stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
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}
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if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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if (TARGET_VSX)
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{
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stmt = build_array_ref (loc, stmt, arg2);
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stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt,
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@ -7035,20 +7035,40 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
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int shift = exact_log2 (width);
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machine_mode idx_mode = GET_MODE (idx);
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idx = convert_modes (DImode, idx_mode, idx, 1);
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machine_mode shift_mode;
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rtx (*gen_ashl)(rtx, rtx, rtx);
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rtx (*gen_lvsl)(rtx, rtx);
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rtx (*gen_lvsr)(rtx, rtx);
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if (TARGET_POWERPC64)
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{
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shift_mode = DImode;
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gen_ashl = gen_ashldi3;
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gen_lvsl = gen_altivec_lvsl_reg_di;
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gen_lvsr = gen_altivec_lvsr_reg_di;
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}
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else
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{
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shift_mode = SImode;
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gen_ashl = gen_ashlsi3;
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gen_lvsl = gen_altivec_lvsl_reg_si;
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gen_lvsr = gen_altivec_lvsr_reg_si;
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}
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/* Generate the IDX for permute shift, width is the vector element size.
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idx = idx * width. */
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_ashldi3 (tmp, idx, GEN_INT (shift)));
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rtx tmp = gen_reg_rtx (shift_mode);
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idx = convert_modes (shift_mode, idx_mode, idx, 1);
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emit_insn (gen_ashl (tmp, idx, GEN_INT (shift)));
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/* lvsr v1,0,idx. */
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rtx pcvr = gen_reg_rtx (V16QImode);
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emit_insn (gen_altivec_lvsr_reg (pcvr, tmp));
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emit_insn (gen_lvsr (pcvr, tmp));
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/* lvsl v2,0,idx. */
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rtx pcvl = gen_reg_rtx (V16QImode);
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emit_insn (gen_altivec_lvsl_reg (pcvl, tmp));
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emit_insn (gen_lvsl (pcvl, tmp));
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rtx sub_target = simplify_gen_subreg (V16QImode, target, mode, 0);
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@ -7064,10 +7084,10 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
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}
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/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
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is variable and also counts by vector element size for p8. */
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is variable and also counts by vector element size for p7 & p8. */
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static void
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rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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rs6000_expand_vector_set_var_p7 (rtx target, rtx val, rtx idx)
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{
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machine_mode mode = GET_MODE (target);
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@ -7082,17 +7102,41 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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int shift = exact_log2 (width);
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machine_mode idx_mode = GET_MODE (idx);
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idx = convert_modes (DImode, idx_mode, idx, 1);
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machine_mode shift_mode;
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rtx (*gen_ashl)(rtx, rtx, rtx);
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rtx (*gen_add)(rtx, rtx, rtx);
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rtx (*gen_sub)(rtx, rtx, rtx);
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rtx (*gen_lvsl)(rtx, rtx);
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if (TARGET_POWERPC64)
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{
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shift_mode = DImode;
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gen_ashl = gen_ashldi3;
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gen_add = gen_adddi3;
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gen_sub = gen_subdi3;
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gen_lvsl = gen_altivec_lvsl_reg_di;
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}
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else
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{
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shift_mode = SImode;
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gen_ashl = gen_ashlsi3;
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gen_add = gen_addsi3;
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gen_sub = gen_subsi3;
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gen_lvsl = gen_altivec_lvsl_reg_si;
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}
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/* idx = idx * width. */
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_ashldi3 (tmp, idx, GEN_INT (shift)));
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rtx tmp = gen_reg_rtx (shift_mode);
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idx = convert_modes (shift_mode, idx_mode, idx, 1);
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emit_insn (gen_ashl (tmp, idx, GEN_INT (shift)));
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/* For LE: idx = idx + 8. */
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if (!BYTES_BIG_ENDIAN)
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emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (8)));
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emit_insn (gen_add (tmp, tmp, GEN_INT (8)));
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else
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emit_insn (gen_subdi3 (tmp, GEN_INT (24 - width), tmp));
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emit_insn (gen_sub (tmp, GEN_INT (24 - width), tmp));
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/* lxv vs33, mask.
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DImode: 0xffffffffffffffff0000000000000000
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@ -7119,7 +7163,16 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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/* mtvsrd[wz] f0,tmp_val. */
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rtx tmp_val = gen_reg_rtx (SImode);
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if (inner_mode == E_SFmode)
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emit_insn (gen_movsi_from_sf (tmp_val, val));
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if (TARGET_DIRECT_MOVE_64BIT)
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emit_insn (gen_movsi_from_sf (tmp_val, val));
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else
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{
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rtx stack = rs6000_allocate_stack_temp (SFmode, false, true);
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emit_insn (gen_movsf_hardfloat (stack, val));
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rtx stack2 = copy_rtx (stack);
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PUT_MODE (stack2, SImode);
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emit_move_insn (tmp_val, stack2);
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}
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else
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tmp_val = force_reg (SImode, val);
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@ -7143,7 +7196,7 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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/* lvsl 13,0,idx. */
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rtx pcv = gen_reg_rtx (V16QImode);
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emit_insn (gen_altivec_lvsl_reg (pcv, tmp));
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emit_insn (gen_lvsl (pcv, tmp));
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/* vperm 1,1,1,13. */
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/* vperm 0,0,0,13. */
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@ -7184,11 +7237,13 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
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rs6000_expand_vector_set_var_p9 (target, val, elt_rtx);
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return;
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}
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else if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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else if (TARGET_VSX)
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{
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rs6000_expand_vector_set_var_p8 (target, val, elt_rtx);
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rs6000_expand_vector_set_var_p7 (target, val, elt_rtx);
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return;
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}
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else
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gcc_assert (CONST_INT_P (elt_rtx));
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}
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rtx insn = NULL_RTX;
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@ -7218,8 +7273,6 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
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}
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}
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gcc_assert (CONST_INT_P (elt_rtx));
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/* Simplify setting single element vectors like V1TImode. */
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if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode)
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&& INTVAL (elt_rtx) == 0)
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@ -1227,7 +1227,7 @@
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(define_expand "vec_set<mode>"
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[(match_operand:VEC_E 0 "vlogical_operand")
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(match_operand:<VEC_base> 1 "register_operand")
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(match_operand 2 "reg_or_cint_operand")]
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(match_operand 2 "vec_set_index_operand")]
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"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
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{
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rs6000_expand_vector_set (operands[0], operands[1], operands[2]);
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@ -5423,7 +5423,7 @@
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rtx rtx_vtmp = gen_reg_rtx (V16QImode);
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_altivec_lvsl_reg (shift_mask, operands[2]));
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emit_insn (gen_altivec_lvsl_reg_di (shift_mask, operands[2]));
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emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
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emit_insn (gen_lxvll (rtx_vtmp, operands[1], tmp));
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emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp, rtx_vtmp,
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@ -5507,7 +5507,7 @@
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rtx rtx_vtmp = gen_reg_rtx (V16QImode);
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_altivec_lvsr_reg (shift_mask, operands[2]));
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emit_insn (gen_altivec_lvsr_reg_di (shift_mask, operands[2]));
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emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0], operands[0],
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shift_mask));
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emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
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@ -58,8 +58,8 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
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/* -m32 codegen. */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 0 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
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@ -54,8 +54,8 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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/* -m32 codegen. */
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/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvebx\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
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@ -24,15 +24,15 @@ testd_cst (double d, vector double vd)
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/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr7 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr7 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr7 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
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@ -29,8 +29,8 @@ testf_cst (float f, vector float vf)
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/* { dg-final { scan-assembler-times {\mvperm\M} 3 { target lp64 } } } */
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/* -m32 codegen. */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 1 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 0 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 2 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 3 { target ilp32 } } } */
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@ -32,4 +32,4 @@ testf_cst (float f, vector float vf)
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/* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 2 { target ilp32 } } } */
|
||||
|
||||
@ -57,7 +57,7 @@ testui2_cst(unsigned int x, vector unsigned int v)
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
|
||||
|
||||
@ -57,9 +57,9 @@ testui2_cst(unsigned int x, vector unsigned int v)
|
||||
/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 8 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxinsertw\M} 8 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstw\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
|
||||
|
||||
@ -65,6 +65,6 @@ testul2_cst(unsigned long long x, vector unsigned long long v)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target ilp32 } } } */
|
||||
|
||||
@ -56,7 +56,7 @@ testus2_cst(unsigned short x, vector unsigned short v)
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
|
||||
|
||||
|
||||
@ -55,10 +55,10 @@ testus2_cst(unsigned short x, vector unsigned short v)
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 0 { target lp64 }} } */
|
||||
|
||||
/* -m32 uses sth/lvehx as part of the sequence. */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 } } } */
|
||||
|
||||
|
||||
15
gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c
Normal file
15
gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c
Normal file
@ -0,0 +1,15 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target vsx_hw } */
|
||||
/* { dg-options "-O2 -mvsx -mdejagnu-cpu=power7" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <altivec.h>
|
||||
#include "pr79251.h"
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
TEST_VEC_INSERT_ALL (run_test)
|
||||
return 0;
|
||||
}
|
||||
|
||||
23
gcc/testsuite/gcc.target/powerpc/pr79251.p7.c
Normal file
23
gcc/testsuite/gcc.target/powerpc/pr79251.p7.c
Normal file
@ -0,0 +1,23 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=power7 -mvsx" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <altivec.h>
|
||||
#include "pr79251.h"
|
||||
|
||||
/* { dg-final { scan-assembler-not {\mstxw\M} } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsl\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsr\M} 3 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 20 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxsel\M} 7 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 19 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvw4x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M} 7 { target ilp32 } } } */
|
||||
|
||||
|
||||
@ -14,9 +14,9 @@
|
||||
/* { dg-final { scan-assembler-times {\mxxsel\M} 7 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvw4x\M} 6 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvw4x\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M} 7 { target ilp32 } } } */
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 7 { target ilp32 } } } */
|
||||
|
||||
|
||||
@ -191,10 +191,11 @@ vector unsigned __int128 splat_uint128 (unsigned __int128 x) { return vec_splats
|
||||
*/
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 0 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target { be && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 4 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 6 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 65 { target { be && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 65 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 33 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 35 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times "vspltisb" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vspltish" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vspltisw" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vspltisw" 2 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times "vspltisw" 23 { target le } } } */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user