h8300.md (bcs type): Remove "bcs" type attribute and all references.
* h8300/h8300.md (bcs type): Remove "bcs" type attribute and
all references.
(bcs insns): Delete. No longer needed.
(setcc from bitfield): Rewrite to use zero_extract. Provide
QImode, HImode and SImode variants.
From-SVN: r11910
This commit is contained in:
Jeff Law
parent
df37d0faf5
commit
e1aa1a6c6e
@ -45,7 +45,7 @@
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;; ??? Implement remaining bit ops available on the h8300
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(define_attr "type" "branch,bcs,arith"
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(define_attr "type" "branch,arith"
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(const_string "arith"))
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;; The size of instructions in bytes.
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@ -63,29 +63,7 @@
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(le (minus (pc) (match_dup 0))
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(const_int 32000))))
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(const_int 4)
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(const_int 6)))
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(eq_attr "type" "bcs")
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(if_then_else (and (ge (minus (pc) (match_dup 0))
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(const_int -120))
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(le (minus (pc) (match_dup 0))
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(const_int 120)))
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(if_then_else
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(match_operand 2 "register_operand" "")
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(const_int 4)
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(const_int 6))
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(if_then_else (and (eq_attr "cpu" "h8300h")
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(and (ge (minus (pc) (match_dup 0))
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(const_int -32000))
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(le (minus (pc) (match_dup 0))
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(const_int 32000))))
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(if_then_else
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(match_operand 2 "register_operand" "")
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(const_int 6)
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(const_int 8))
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(if_then_else
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(match_operand 2 "register_operand" "")
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(const_int 8)
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(const_int 10))))]
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(const_int 6)))]
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(const_int 200)))
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;; Condition code settings.
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@ -460,10 +438,29 @@
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;; ----------------------------------------------------------------------
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(define_insn ""
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[(set (cc0) (and:QI (match_operand:QI 0 "bit_operand" "Ur")
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(match_operand:QI 1 "o_operand" "O")))]
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[(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 1 "const_int_operand" "n")))]
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""
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"btst %W1,%R0"
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"btst %Z1,%R0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(define_insn ""
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[(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 1 "const_int_operand" "n")))]
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(define_insn ""
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[(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 1 "const_int_operand" "n")))]
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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@ -1825,148 +1822,6 @@
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;; The H8/300 has given 1/8th of its opcode space to bitfield
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;; instructions so let's use them as well as we can.
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;; BCC and BCS patterns.
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 1 "eq_operator"
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[(zero_extract:QI
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(match_operand:HI 2 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 3 "immediate_operand" "i"))
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(const_int 0)])
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"*
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{
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/* The length of this insn includes the bld insn below. We
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compute the length of the branch without the bld so we
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can easily choose the right branch length. */
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int branch_length = get_attr_length (insn);
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if (! register_operand (operands[2], HImode))
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branch_length -= 4;
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else
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branch_length -= 2;
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output_asm_insn(\"bld %Z3,%Y2\", operands);
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if (branch_length == 2)
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return \"%d1 %l0\";
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else if (branch_length == 4)
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return \"%d1 %l0:16\";
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else
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return \"%g1 %L0\;jmp @%l0\;%L0:\";
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}"
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[(set_attr "type" "bcs")
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(set_attr "cc" "clobber")])
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 1 "eq_operator"
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[(zero_extract:HI
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(match_operand:HI 2 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 3 "immediate_operand" "i"))
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(const_int 0)])
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"*
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{
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/* The length of this insn includes the bld insn below. We
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compute the length of the branch without the bld so we
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can easily choose the right branch length. */
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int branch_length = get_attr_length (insn);
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if (! register_operand (operands[2], HImode))
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branch_length -= 4;
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else
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branch_length -= 2;
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output_asm_insn(\"bld %Z3,%Y2\", operands);
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if (branch_length == 2)
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return \"%d1 %l0\";
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else if (branch_length == 4)
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return \"%d1 %l0:16\";
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else
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return \"%g1 %L0\;jmp @%l0\;%L0:\";
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}"
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[(set_attr "type" "bcs")
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(set_attr "cc" "clobber")])
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 1 "eq_operator"
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[(zero_extract:HI
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(match_operand:HI 2 "register_operand" "U")
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(const_int 1)
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(match_operand:HI 3 "immediate_operand" "i"))
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(const_int 0)])
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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""
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"*
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{
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/* The length of this insn includes the bld insn below. We
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compute the length of the branch without the bld so we
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can easily choose the right branch length. */
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int branch_length = get_attr_length (insn);
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if (! register_operand (operands[2], HImode))
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branch_length -= 4;
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else
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branch_length -= 2;
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output_asm_insn(\"bld %Z3,%Y2\", operands);
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if (branch_length == 2)
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return \"%d1 %l0\";
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else if (branch_length == 4)
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return \"%d1 %l0:16\";
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else
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return \"%g1 %L0\;jmp @%l0\;%L0:\";
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}"
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[(set_attr "type" "bcs")
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(set_attr "cc" "clobber")])
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 1 "eq_operator"
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[(zero_extract:QI
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(match_operand:HI 2 "register_operand" "r")
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(const_int 1)
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(match_operand:HI 3 "immediate_operand" "i"))
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(const_int 0)])
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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""
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"*
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{
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/* The length of this insn includes the bld insn below. We
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compute the length of the branch without the bld so we
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can easily choose the right branch length. */
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int branch_length = get_attr_length (insn);
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if (! register_operand (operands[2], HImode))
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branch_length -= 4;
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else
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branch_length -= 2;
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output_asm_insn(\"bld %Z3,%Y2\", operands);
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if (branch_length == 2)
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return \"%d1 %l0\";
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else if (branch_length == 4)
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return \"%d1 %l0:16\";
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else
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return \"%g1 %L0\;jmp @%l0\;%L0:\";
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}"
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[(set_attr "type" "bcs")
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(set_attr "cc" "clobber")])
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;; You'll never believe all these patterns perform one basic action --
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;; load a bit from the source, optionally invert the bit, then store it
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;; in the destination (which is known to be zero)..
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