[arm] Put CPU's FPU capabilities directly in the ISA specification
As part of the transition from the original support for named FPUs to general FPU properties I defined an entry in the CPU definitions in arm-cpus.in to use a named FPU. However, that has now outlived its usefulness and increasingly we are likely to find that newer cores do not fit the legacy FPU names very well. Furthermore it is now possible to encode all the FPU capatilities directly in the ISA definitions, often as simply as using +fp or +simd. So this patch removes the fpu field from the "define cpu" entries and instead encodes the same information in the isa field. This also alows us to remove a bit of now-dead code from parsecpu.awk. * config/arm/arm-cpus.in: Move information from fpu field of each cpu definition to the isa field. * config/arm/parsecpu.awk (fpu): Delete match rule. (gen_comm_data): Don't add bits from the CPU's FPU entry. From-SVN: r262556
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
305130b92e
commit
dff2abcbee
@ -1,3 +1,10 @@
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2018-07-11 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm-cpus.in: Move information from fpu field of each
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cpu definition to the isa field.
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* config/arm/parsecpu.awk (fpu): Delete match rule.
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(gen_comm_data): Don't add bits from the CPU's FPU entry.
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2018-07-11 Richard Biener <rguenther@suse.de>
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PR debug/86457
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@ -620,7 +620,6 @@ end arch iwmmxt2
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# [tune for <cpu-name>]
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# [tune flags <list>]
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# architecture <name>
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# [fpu <name>]
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# [isa <additional-isa-flags-list>]
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# [option <name> add|remove <isa-list>]*
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# [optalias <name> <optname>]*
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@ -633,7 +632,7 @@ end arch iwmmxt2
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# isa flags are appended to those defined by the architecture.
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# Each add option must have a distinct feature set and each remove
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# option must similarly have a distinct feature set. Option aliases can be
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# added with the optalias statement
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# added with the optalias statement.
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# V4 Architecture Processors
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begin cpu arm8
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@ -778,8 +777,7 @@ end cpu arm1020t
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# V5TE Architecture Processors
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begin cpu arm9e
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm9e
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@ -787,8 +785,7 @@ end cpu arm9e
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begin cpu arm946e-s
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cname arm946es
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm946e-s
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@ -796,8 +793,7 @@ end cpu arm946e-s
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begin cpu arm966e-s
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cname arm966es
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm966e-s
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@ -805,32 +801,28 @@ end cpu arm966e-s
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begin cpu arm968e-s
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cname arm968es
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm968e-s
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begin cpu arm10e
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm10e
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begin cpu arm1020e
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm1020e
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begin cpu arm1022e
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tune flags LDSCHED
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architecture armv5te
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fpu vfpv2
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm1022e
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@ -883,8 +875,7 @@ end cpu fa726te
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begin cpu arm926ej-s
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cname arm926ejs
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tune flags LDSCHED
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architecture armv5tej
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fpu vfpv2
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architecture armv5tej+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm926ej-s
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@ -892,8 +883,7 @@ end cpu arm926ej-s
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begin cpu arm1026ej-s
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cname arm1026ejs
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tune flags LDSCHED
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architecture armv5tej
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fpu vfpv2
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architecture armv5tej+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm1026ej-s
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@ -910,8 +900,7 @@ end cpu arm1136j-s
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begin cpu arm1136jf-s
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cname arm1136jfs
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tune flags LDSCHED
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architecture armv6j
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fpu vfpv2
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architecture armv6j+fp
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costs 9e
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end cpu arm1136jf-s
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@ -925,8 +914,7 @@ end cpu arm1176jz-s
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begin cpu arm1176jzf-s
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cname arm1176jzfs
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tune flags LDSCHED
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architecture armv6kz
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fpu vfpv2
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architecture armv6kz+fp
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costs 9e
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end cpu arm1176jzf-s
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@ -938,8 +926,7 @@ end cpu mpcorenovfp
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begin cpu mpcore
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tune flags LDSCHED
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architecture armv6k
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fpu vfpv2
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architecture armv6k+fp
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costs 9e
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end cpu mpcore
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@ -953,8 +940,7 @@ end cpu arm1156t2-s
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begin cpu arm1156t2f-s
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cname arm1156t2fs
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tune flags LDSCHED
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architecture armv6t2
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fpu vfpv2
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architecture armv6t2+fp
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costs v6t2
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end cpu arm1156t2f-s
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@ -1012,8 +998,7 @@ end cpu cortex-m0plus.small-multiply
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begin cpu generic-armv7-a
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cname genericv7a
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tune flags LDSCHED
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architecture armv7-a
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fpu vfpv3-d16
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architecture armv7-a+fp
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option vfpv3-d16 add VFPv3 FP_DBL
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option vfpv3 add VFPv3 FP_D32
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option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
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@ -1033,8 +1018,7 @@ end cpu generic-armv7-a
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begin cpu cortex-a5
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cname cortexa5
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tune flags LDSCHED
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architecture armv7-a
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fpu neon-fp16
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architecture armv7-a+neon-fp16
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option nosimd remove ALL_SIMD
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option nofp remove ALL_FP
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costs cortex_a5
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@ -1043,8 +1027,7 @@ end cpu cortex-a5
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begin cpu cortex-a7
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cname cortexa7
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nosimd remove ALL_SIMD
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option nofp remove ALL_FP
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costs cortex_a7
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@ -1053,8 +1036,7 @@ end cpu cortex-a7
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begin cpu cortex-a8
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cname cortexa8
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tune flags LDSCHED
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architecture armv7-a
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fpu neon-vfpv3
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architecture armv7-a+simd
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option nofp remove ALL_FP
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costs cortex_a8
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end cpu cortex-a8
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@ -1062,8 +1044,7 @@ end cpu cortex-a8
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begin cpu cortex-a9
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cname cortexa9
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tune flags LDSCHED
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architecture armv7-a
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fpu neon-fp16
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architecture armv7-a+neon-fp16
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option nosimd remove ALL_SIMD
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option nofp remove ALL_FP
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costs cortex_a9
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@ -1073,8 +1054,7 @@ begin cpu cortex-a12
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cname cortexa12
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tune for cortex-a17
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nofp remove ALL_FP
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costs cortex_a12
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end cpu cortex-a12
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@ -1082,8 +1062,7 @@ end cpu cortex-a12
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begin cpu cortex-a15
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cname cortexa15
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nofp remove ALL_FP
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costs cortex_a15
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end cpu cortex-a15
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@ -1091,8 +1070,7 @@ end cpu cortex-a15
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begin cpu cortex-a17
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cname cortexa17
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nofp remove ALL_FP
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costs cortex_a12
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end cpu cortex-a17
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@ -1107,16 +1085,14 @@ end cpu cortex-r4
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begin cpu cortex-r4f
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cname cortexr4f
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tune flags LDSCHED
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architecture armv7-r
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fpu vfpv3-d16
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architecture armv7-r+fp
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costs cortex
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end cpu cortex-r4f
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begin cpu cortex-r5
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cname cortexr5
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tune flags LDSCHED
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architecture armv7-r+idiv
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fpu vfpv3-d16
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architecture armv7-r+idiv+fp
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option nofp.dp remove FP_DBL
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option nofp remove ALL_FP
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costs cortex
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@ -1125,8 +1101,7 @@ end cpu cortex-r5
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begin cpu cortex-r7
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cname cortexr7
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tune flags LDSCHED
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architecture armv7-r+idiv
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fpu vfpv3-d16
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architecture armv7-r+idiv+fp
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option nofp remove ALL_FP
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costs cortex
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end cpu cortex-r7
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@ -1135,8 +1110,7 @@ begin cpu cortex-r8
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cname cortexr8
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tune for cortex-r7
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tune flags LDSCHED
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architecture armv7-r+idiv
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fpu vfpv3-d16
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architecture armv7-r+idiv+fp
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option nofp remove ALL_FP
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costs cortex
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end cpu cortex-r8
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@ -1144,9 +1118,8 @@ end cpu cortex-r8
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begin cpu cortex-m7
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cname cortexm7
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tune flags LDSCHED
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architecture armv7e-m
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architecture armv7e-m+fp.dp
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isa quirk_no_volatile_ce
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fpu fpv5-d16
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option nofp.dp remove FP_DBL
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option nofp remove ALL_FP
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costs cortex_m7
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@ -1155,8 +1128,7 @@ end cpu cortex-m7
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begin cpu cortex-m4
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cname cortexm4
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tune flags LDSCHED
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architecture armv7e-m
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fpu fpv4-sp-d16
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architecture armv7e-m+fp
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option nofp remove ALL_FP
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costs v7m
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end cpu cortex-m4
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@ -1181,8 +1153,7 @@ begin cpu cortex-a15.cortex-a7
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cname cortexa15cortexa7
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tune for cortex-a7
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nofp remove ALL_FP
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costs cortex_a15
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end cpu cortex-a15.cortex-a7
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@ -1191,8 +1162,7 @@ begin cpu cortex-a17.cortex-a7
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cname cortexa17cortexa7
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tune for cortex-a7
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tune flags LDSCHED
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architecture armv7ve
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fpu neon-vfpv4
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architecture armv7ve+simd
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option nofp remove ALL_FP
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costs cortex_a12
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end cpu cortex-a17.cortex-a7
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@ -1203,8 +1173,7 @@ begin cpu cortex-a32
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cname cortexa32
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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option nofp remove ALL_FP
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costs cortex_a35
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@ -1214,8 +1183,7 @@ begin cpu cortex-a35
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cname cortexa35
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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option nofp remove ALL_FP
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costs cortex_a35
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@ -1224,8 +1192,7 @@ end cpu cortex-a35
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begin cpu cortex-a53
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cname cortexa53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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option nofp remove ALL_FP
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costs cortex_a53
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@ -1234,8 +1201,7 @@ end cpu cortex-a53
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begin cpu cortex-a57
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cname cortexa57
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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end cpu cortex-a57
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@ -1244,8 +1210,7 @@ begin cpu cortex-a72
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cname cortexa72
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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end cpu cortex-a72
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@ -1254,8 +1219,7 @@ begin cpu cortex-a73
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cname cortexa73
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a73
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end cpu cortex-a73
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@ -1263,16 +1227,14 @@ end cpu cortex-a73
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begin cpu exynos-m1
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cname exynosm1
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs exynosm1
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end cpu exynos-m1
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begin cpu xgene1
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tune flags LDSCHED
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architecture armv8-a
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fpu neon-fp-armv8
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architecture armv8-a+simd
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option crypto add FP_ARMv8 CRYPTO
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costs xgene1
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end cpu xgene1
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@ -1282,8 +1244,7 @@ begin cpu cortex-a57.cortex-a53
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cname cortexa57cortexa53
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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end cpu cortex-a57.cortex-a53
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@ -1292,8 +1253,7 @@ begin cpu cortex-a72.cortex-a53
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cname cortexa72cortexa53
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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end cpu cortex-a72.cortex-a53
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@ -1302,8 +1262,7 @@ begin cpu cortex-a73.cortex-a35
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cname cortexa73cortexa35
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a73
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end cpu cortex-a73.cortex-a35
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@ -1312,8 +1271,7 @@ begin cpu cortex-a73.cortex-a53
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cname cortexa73cortexa53
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8-a+crc
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fpu neon-fp-armv8
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architecture armv8-a+crc+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a73
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end cpu cortex-a73.cortex-a53
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@ -1324,8 +1282,7 @@ begin cpu cortex-a55
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cname cortexa55
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8.2-a+fp16+dotprod
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fpu neon-fp-armv8
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architecture armv8.2-a+fp16+dotprod+simd
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option crypto add FP_ARMv8 CRYPTO
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option nofp remove ALL_FP
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costs cortex_a53
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@ -1335,8 +1292,7 @@ begin cpu cortex-a75
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cname cortexa75
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8.2-a+fp16+dotprod
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fpu neon-fp-armv8
|
||||
architecture armv8.2-a+fp16+dotprod+simd
|
||||
option crypto add FP_ARMv8 CRYPTO
|
||||
costs cortex_a73
|
||||
end cpu cortex-a75
|
||||
@ -1345,8 +1301,7 @@ begin cpu cortex-a76
|
||||
cname cortexa76
|
||||
tune for cortex-a57
|
||||
tune flags LDSCHED
|
||||
architecture armv8.2-a+fp16+dotprod
|
||||
fpu neon-fp-armv8
|
||||
architecture armv8.2-a+fp16+dotprod+simd
|
||||
option crypto add FP_ARMv8 CRYPTO
|
||||
costs cortex_a57
|
||||
end cpu cortex-a76
|
||||
@ -1356,8 +1311,7 @@ begin cpu cortex-a75.cortex-a55
|
||||
cname cortexa75cortexa55
|
||||
tune for cortex-a53
|
||||
tune flags LDSCHED
|
||||
architecture armv8.2-a+fp16+dotprod
|
||||
fpu neon-fp-armv8
|
||||
architecture armv8.2-a+fp16+dotprod+simd
|
||||
option crypto add FP_ARMv8 CRYPTO
|
||||
costs cortex_a73
|
||||
end cpu cortex-a75.cortex-a55
|
||||
@ -1366,8 +1320,7 @@ begin cpu cortex-a76.cortex-a55
|
||||
cname cortexa76cortexa55
|
||||
tune for cortex-a53
|
||||
tune flags LDSCHED
|
||||
architecture armv8.2-a+fp16+dotprod
|
||||
fpu neon-fp-armv8
|
||||
architecture armv8.2-a+fp16+dotprod+simd
|
||||
option crypto add FP_ARMv8 CRYPTO
|
||||
costs cortex_a57
|
||||
end cpu cortex-a76.cortex-a55
|
||||
@ -1383,8 +1336,7 @@ end cpu cortex-m23
|
||||
begin cpu cortex-m33
|
||||
cname cortexm33
|
||||
tune flags LDSCHED
|
||||
architecture armv8-m.main+dsp
|
||||
fpu fpv5-sp-d16
|
||||
architecture armv8-m.main+dsp+fp
|
||||
option nofp remove ALL_FP
|
||||
option nodsp remove armv7em
|
||||
costs v7m
|
||||
@ -1395,7 +1347,6 @@ begin cpu cortex-r52
|
||||
cname cortexr52
|
||||
tune flags LDSCHED
|
||||
architecture armv8-r+crc+simd
|
||||
fpu neon-fp-armv8
|
||||
option nofp.dp remove FP_DBL ALL_SIMD
|
||||
costs cortex
|
||||
end cpu cortex-r52
|
||||
|
||||
@ -289,9 +289,6 @@ function gen_comm_data () {
|
||||
}
|
||||
all_isa_bits = all_isa_bits " " arch_opt_isa[feats[1],feats[m]]
|
||||
}
|
||||
if (cpus[n] in cpu_fpu) {
|
||||
all_isa_bits = all_isa_bits " " fpu_isa[cpu_fpu[cpus[n]]]
|
||||
}
|
||||
if (cpus[n] in cpu_isa) {
|
||||
all_isa_bits = all_isa_bits " " cpu_isa[cpus[n]]
|
||||
}
|
||||
@ -662,13 +659,6 @@ BEGIN {
|
||||
parse_ok = 1
|
||||
}
|
||||
|
||||
/^[ ]*fpu / {
|
||||
if (NF != 2) fatal("syntax: fpu <fpu-name>")
|
||||
if (cpu_name == "") fatal("\"fpu\" outside of cpu block")
|
||||
cpu_fpu[cpu_name] = $2
|
||||
parse_ok = 1
|
||||
}
|
||||
|
||||
/^[ ]*isa / {
|
||||
if (NF < 2) fatal("syntax: isa <feature-or-fgroup> [<feature-or-fgroup>]*")
|
||||
flags=""
|
||||
|
||||
Loading…
Reference in New Issue
Block a user