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New anonymous patterns to combine insert with arbitrary ashift, ashiftrt,

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lshiftrt, or zero_extract.  (Based on patch from John Brooks <jbrooks@ea.com>.)
(ashlsi3): Remove extraneous operand processing.

From-SVN: r9523
This commit is contained in:
Richard Kenner 1995-04-27 21:10:25 -04:00
parent 6eaba4a70a
commit d56d506a92
1 changed files with 83 additions and 3 deletions
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86
gcc/config/rs6000/rs6000.md
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@ -1935,6 +1935,82 @@
return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")))]
""
"*
{
int shift = INTVAL (operands[4]) & 31;
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")))]
""
"*
{
int shift = INTVAL (operands[4]) & 31;
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")))]
""
"*
{
int shift = INTVAL (operands[4]) & 31;
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")
(match_operand:SI 5 "const_int_operand" "i")))]
"INTVAL (operands[4]) >= INTVAL (operands[1])"
"*
{
int extract_start = INTVAL (operands[5]) & 31;
int extract_size = INTVAL (operands[4]) & 31;
int insert_start = INTVAL (operands[2]) & 31;
int insert_size = INTVAL (operands[1]) & 31;
/* Align extract field with insert field */
operands[5] = gen_rtx (CONST_INT, VOIDmode,
(extract_start + extract_size - insert_start - insert_size) & 31);
operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
}")
(define_insn "extzv"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@ -2238,7 +2314,7 @@
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3")
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
@ -2249,7 +2325,7 @@
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3"
"{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
(define_insn ""
@ -2262,7 +2338,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3"
"{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
;; The AIX assembler mis-handles "sri x,x,0", so write that case as
@ -2928,6 +3004,7 @@
}
DONE;
}")
(define_insn "fselsfsf4"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
@ -2947,6 +3024,7 @@
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
@ -3173,6 +3251,7 @@
}
DONE;
}")
(define_insn "fseldfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
@ -3182,6 +3261,7 @@
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "fselsfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")