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i386: Merge various insn name mapping code attributes

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2021-01-07  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
	* config/i386/i386.md (insn): Merge from plusminus_insn, shift_insn,
	rotate_insn and optab code attributes.
	Update all uses to merged code attribute.
	* config/i386/sse.md: Update all uses to merged code attribute.
	* config/i386/mmx.md: Update all uses to merged code attribute.
This commit is contained in:
Uros Bizjak 2021-01-07 14:39:02 +01:00
parent d02a8b63e5
commit d54be5ad21
3 changed files with 94 additions and 99 deletions
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97
gcc/config/i386/i386.md
View File

@ -869,7 +869,8 @@
(eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
(eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
(eq_attr "isa" "avxvnni") (symbol_ref "TARGET_AVXVNNI")
(eq_attr "isa" "avx512vnnivl") (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL")
(eq_attr "isa" "avx512vnnivl")
(symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL")
(eq_attr "mmx_isa" "native")
(symbol_ref "!TARGET_MMX_WITH_SSE")
@ -894,17 +895,13 @@
(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
(define_code_iterator multdiv [mult div])
;; Base name for define_insn
(define_code_attr plusminus_insn
[(plus "add") (ss_plus "ssadd") (us_plus "usadd")
(minus "sub") (ss_minus "sssub") (us_minus "ussub")])
;; Base name for insn mnemonic.
(define_code_attr plusminus_mnemonic
[(plus "add") (ss_plus "adds") (us_plus "addus")
(minus "sub") (ss_minus "subs") (us_minus "subus")])
(define_code_iterator multdiv [mult div])
(define_code_attr multdiv_mnemonic
[(mult "mul") (div "div")])
@ -951,10 +948,6 @@
;; Mapping of all shift operators
(define_code_iterator any_shift [ashift lshiftrt ashiftrt])
;; Base name for define_insn
(define_code_attr shift_insn
[(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
;; Base name for insn mnemonic.
(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
@ -962,9 +955,6 @@
;; Mapping of rotate operators
(define_code_iterator any_rotate [rotate rotatert])
;; Base name for define_insn
(define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")])
;; Base name for insn mnemonic.
(define_code_attr rotate [(rotate "rol") (rotatert "ror")])
@ -977,13 +967,9 @@
;; Base name for x87 insn mnemonic.
(define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")])
;; Used in signed and unsigned widening multiplications.
;; Mapping of extend operators
(define_code_iterator any_extend [sign_extend zero_extend])
;; Used for representing standard name for extend
(define_code_attr optab [(sign_extend "extend")
(zero_extend "zero_extend")])
;; Prefix for insn menmonic.
(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")
(div "i") (udiv "")])
@ -997,7 +983,8 @@
;; Used in signed and unsigned truncations.
(define_code_iterator any_truncate [ss_truncate truncate us_truncate])
;; Instruction suffix for truncations.
(define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")])
(define_code_attr trunsuffix
[(ss_truncate "s") (truncate "") (us_truncate "us")])
;; Used in signed and unsigned fix.
(define_code_iterator any_fix [fix unsigned_fix])
@ -1011,6 +998,14 @@
(define_code_attr floatunssuffix [(float "") (unsigned_float "uns")])
(define_code_attr floatprefix [(float "s") (unsigned_float "u")])
;; Base name for expression
(define_code_attr insn
[(plus "add") (ss_plus "ssadd") (us_plus "usadd")
(minus "sub") (ss_minus "sssub") (us_minus "ussub")
(sign_extend "extend") (zero_extend "zero_extend")
(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")
(rotate "rotl") (rotatert "rotr")])
;; All integer modes.
(define_mode_iterator SWI1248x [QI HI SI DI])
@ -7460,14 +7455,14 @@
;; The patterns that match these are at the end of this file.
(define_expand "<plusminus_insn>xf3"
(define_expand "<insn>xf3"
[(set (match_operand:XF 0 "register_operand")
(plusminus:XF
(match_operand:XF 1 "register_operand")
(match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "<plusminus_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:MODEF 0 "register_operand")
(plusminus:MODEF
(match_operand:MODEF 1 "register_operand")
@ -11399,7 +11394,7 @@
;; See comment above `ashl<mode>3' about how this works.
(define_expand "<shift_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:SDWIM 0 "<shift_operand>")
(any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>")
(match_operand:QI 2 "nonmemory_operand")))]
@ -11407,7 +11402,7 @@
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
;; Avoid useless masking of count operand.
(define_insn_and_split "*<shift_insn><mode>3_mask"
(define_insn_and_split "*<insn><mode>3_mask"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
@ -11430,7 +11425,7 @@
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*<shift_insn><mode>3_mask_1"
(define_insn_and_split "*<insn><mode>3_mask_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
@ -11452,7 +11447,7 @@
""
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask"
(define_insn_and_split "*<insn><dwi>3_doubleword_mask"
[(set (match_operand:<DWI> 0 "register_operand")
(any_shiftrt:<DWI>
(match_operand:<DWI> 1 "register_operand")
@ -11494,7 +11489,7 @@
emit_move_insn (operands[4], operands[5]);
})
(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask_1"
(define_insn_and_split "*<insn><dwi>3_doubleword_mask_1"
[(set (match_operand:<DWI> 0 "register_operand")
(any_shiftrt:<DWI>
(match_operand:<DWI> 1 "register_operand")
@ -11533,7 +11528,7 @@
emit_move_insn (operands[4], operands[5]);
})
(define_insn_and_split "*<shift_insn><mode>3_doubleword"
(define_insn_and_split "*<insn><mode>3_doubleword"
[(set (match_operand:DWI 0 "register_operand" "=&r")
(any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "<S>c")))
@ -11542,7 +11537,7 @@
"#"
"epilogue_completed"
[(const_int 0)]
"ix86_split_<shift_insn> (operands, NULL_RTX, <MODE>mode); DONE;"
"ix86_split_<insn> (operands, NULL_RTX, <MODE>mode); DONE;"
[(set_attr "type" "multi")])
;; By default we don't ask for a scratch register, because when DWImode
@ -11559,7 +11554,7 @@
(match_dup 3)]
"TARGET_CMOVE"
[(const_int 0)]
"ix86_split_<shift_insn> (operands, operands[3], <DWI>mode); DONE;")
"ix86_split_<insn> (operands, operands[3], <DWI>mode); DONE;")
(define_insn "x86_64_shrd"
[(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
@ -11663,7 +11658,7 @@
DONE;
})
(define_insn "*bmi2_<shift_insn><mode>3_1"
(define_insn "*bmi2_<insn><mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 2 "register_operand" "r")))]
@ -11672,7 +11667,7 @@
[(set_attr "type" "ishiftx")
(set_attr "mode" "<MODE>")])
(define_insn "*<shift_insn><mode>3_1"
(define_insn "*<insn><mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
@ -11715,7 +11710,7 @@
(any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
"operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
(define_insn "*bmi2_<shift_insn>si3_1_zext"
(define_insn "*bmi2_<insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
@ -11725,7 +11720,7 @@
[(set_attr "type" "ishiftx")
(set_attr "mode" "SI")])
(define_insn "*<shift_insn>si3_1_zext"
(define_insn "*<insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
@ -11769,7 +11764,7 @@
(zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"operands[2] = gen_lowpart (SImode, operands[2]);")
(define_insn "*<shift_insn><mode>3_1"
(define_insn "*<insn><mode>3_1"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
(any_shiftrt:SWI12
(match_operand:SWI12 1 "nonimmediate_operand" "0")
@ -11793,7 +11788,7 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
(define_insn "*<shift_insn><mode>3_1_slp"
(define_insn "*<insn><mode>3_1_slp"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
(any_shiftrt:SWI12 (match_operand:SWI12 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "cI")))
@ -11821,7 +11816,7 @@
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*<shift_insn><mode>3_cmp"
(define_insn "*<insn><mode>3_cmp"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SWI
@ -11853,7 +11848,7 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
(define_insn "*<shift_insn>si3_cmp_zext"
(define_insn "*<insn>si3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
@ -11885,7 +11880,7 @@
(const_string "*")))
(set_attr "mode" "SI")])
(define_insn "*<shift_insn><mode>3_cconly"
(define_insn "*<insn><mode>3_cconly"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SWI
@ -11917,14 +11912,14 @@
;; Rotate instructions
(define_expand "<rotate_insn>ti3"
(define_expand "<insn>ti3"
[(set (match_operand:TI 0 "register_operand")
(any_rotate:TI (match_operand:TI 1 "register_operand")
(match_operand:QI 2 "nonmemory_operand")))]
"TARGET_64BIT"
{
if (const_1_to_63_operand (operands[2], VOIDmode))
emit_insn (gen_ix86_<rotate_insn>ti3_doubleword
emit_insn (gen_ix86_<insn>ti3_doubleword
(operands[0], operands[1], operands[2]));
else
FAIL;
@ -11932,7 +11927,7 @@
DONE;
})
(define_expand "<rotate_insn>di3"
(define_expand "<insn>di3"
[(set (match_operand:DI 0 "shiftdi_operand")
(any_rotate:DI (match_operand:DI 1 "shiftdi_operand")
(match_operand:QI 2 "nonmemory_operand")))]
@ -11941,7 +11936,7 @@
if (TARGET_64BIT)
ix86_expand_binary_operator (<CODE>, DImode, operands);
else if (const_1_to_31_operand (operands[2], VOIDmode))
emit_insn (gen_ix86_<rotate_insn>di3_doubleword
emit_insn (gen_ix86_<insn>di3_doubleword
(operands[0], operands[1], operands[2]));
else
FAIL;
@ -11949,7 +11944,7 @@
DONE;
})
(define_expand "<rotate_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:SWIM124 0 "nonimmediate_operand")
(any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand")
(match_operand:QI 2 "nonmemory_operand")))]
@ -11957,7 +11952,7 @@
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
;; Avoid useless masking of count operand.
(define_insn_and_split "*<rotate_insn><mode>3_mask"
(define_insn_and_split "*<insn><mode>3_mask"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
@ -11995,7 +11990,7 @@
(subreg:QI (match_dup 2) 0)))]
"operands[4] = gen_reg_rtx (<MODE>mode);")
(define_insn_and_split "*<rotate_insn><mode>3_mask_1"
(define_insn_and_split "*<insn><mode>3_mask_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
@ -12102,7 +12097,7 @@
[(set_attr "type" "rotatex")
(set_attr "mode" "<MODE>")])
(define_insn "*<rotate_insn><mode>3_1"
(define_insn "*<insn><mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
@ -12169,7 +12164,7 @@
[(set_attr "type" "rotatex")
(set_attr "mode" "SI")])
(define_insn "*<rotate_insn>si3_1_zext"
(define_insn "*<insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
@ -12228,7 +12223,7 @@
[(set (match_dup 0)
(zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))])
(define_insn "*<rotate_insn><mode>3_1"
(define_insn "*<insn><mode>3_1"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
(any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "c<S>")))
@ -12251,7 +12246,7 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
(define_insn "*<rotate_insn><mode>3_1_slp"
(define_insn "*<insn><mode>3_1_slp"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
(any_rotate:SWI12 (match_operand:SWI12 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "cI")))

14
gcc/config/i386/mmx.md
View File

@ -1135,7 +1135,7 @@
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_<plusminus_insn><mode>3"
(define_expand "mmx_<insn><mode>3"
[(set (match_operand:MMXMODEI8 0 "register_operand")
(plusminus:MMXMODEI8
(match_operand:MMXMODEI8 1 "register_mmxmem_operand")
@ -1143,7 +1143,7 @@
"TARGET_MMX || TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_expand "<plusminus_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:MMXMODEI 0 "register_operand")
(plusminus:MMXMODEI
(match_operand:MMXMODEI 1 "register_operand")
@ -1151,7 +1151,7 @@
"TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*mmx_<plusminus_insn><mode>3"
(define_insn "*mmx_<insn><mode>3"
[(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv")
(plusminus:MMXMODEI8
(match_operand:MMXMODEI8 1 "register_mmxmem_operand" "<comm>0,0,Yv")
@ -1167,7 +1167,7 @@
(set_attr "type" "mmxadd,sseadd,sseadd")
(set_attr "mode" "DI,TI,TI")])
(define_expand "mmx_<plusminus_insn><mode>3"
(define_expand "mmx_<insn><mode>3"
[(set (match_operand:MMXMODE12 0 "register_operand")
(sat_plusminus:MMXMODE12
(match_operand:MMXMODE12 1 "register_mmxmem_operand")
@ -1175,7 +1175,7 @@
"TARGET_MMX || TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*mmx_<plusminus_insn><mode>3"
(define_insn "*mmx_<insn><mode>3"
[(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv")
(sat_plusminus:MMXMODE12
(match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yv")
@ -1508,7 +1508,7 @@
(match_operand:DI 2 "nonmemory_operand")))]
"TARGET_MMX_WITH_SSE")
(define_insn "mmx_<shift_insn><mode>3"
(define_insn "mmx_<insn><mode>3"
[(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")
(any_lshift:MMXMODE248
(match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")
@ -1527,7 +1527,7 @@
(const_string "0")))
(set_attr "mode" "DI,TI,TI")])
(define_expand "<shift_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:MMXMODE248 0 "register_operand")
(any_lshift:MMXMODE248
(match_operand:MMXMODE248 1 "register_operand")

82
gcc/config/i386/sse.md
View File

@ -1854,7 +1854,7 @@
}
[(set_attr "isa" "noavx,noavx,avx,avx")])
(define_expand "<plusminus_insn><mode>3<mask_name><round_name>"
(define_expand "<insn><mode>3<mask_name><round_name>"
[(set (match_operand:VF 0 "register_operand")
(plusminus:VF
(match_operand:VF 1 "<round_nimm_predicate>")
@ -1862,7 +1862,7 @@
"TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<plusminus_insn><mode>3<mask_name><round_name>"
(define_insn "*<insn><mode>3<mask_name><round_name>"
[(set (match_operand:VF 0 "register_operand" "=x,v")
(plusminus:VF
(match_operand:VF 1 "<bcst_round_nimm_predicate>" "<comm>0,v")
@ -1879,7 +1879,7 @@
;; Standard scalar operation patterns which preserve the rest of the
;; vector for combiner.
(define_insn "*<sse>_vm<plusminus_insn><mode>3"
(define_insn "*<sse>_vm<insn><mode>3"
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
(vec_merge:VF_128
(vec_duplicate:VF_128
@ -1899,7 +1899,7 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "<sse>_vm<plusminus_insn><mode>3<mask_scalar_name><round_scalar_name>"
(define_insn "<sse>_vm<insn><mode>3<mask_scalar_name><round_scalar_name>"
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
(vec_merge:VF_128
(plusminus:VF_128
@ -2569,7 +2569,7 @@
operands[5] = GEN_INT (ival);
})
(define_insn "avx_h<plusminus_insn>v4df3"
(define_insn "avx_h<insn>v4df3"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(vec_concat:V4DF
(vec_concat:V2DF
@ -2698,7 +2698,7 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
(define_insn "avx_h<plusminus_insn>v8sf3"
(define_insn "avx_h<insn>v8sf3"
[(set (match_operand:V8SF 0 "register_operand" "=x")
(vec_concat:V8SF
(vec_concat:V4SF
@ -2741,7 +2741,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
(define_insn "sse3_h<plusminus_insn>v4sf3"
(define_insn "sse3_h<insn>v4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_concat:V4SF
(vec_concat:V2SF
@ -11489,7 +11489,7 @@
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "<plusminus_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:VI_AVX2 0 "register_operand")
(plusminus:VI_AVX2
(match_operand:VI_AVX2 1 "vector_operand")
@ -11497,7 +11497,7 @@
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_expand "<plusminus_insn><mode>3_mask"
(define_expand "<insn><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand")
(vec_merge:VI48_AVX512VL
(plusminus:VI48_AVX512VL
@ -11508,7 +11508,7 @@
"TARGET_AVX512F"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_expand "<plusminus_insn><mode>3_mask"
(define_expand "<insn><mode>3_mask"
[(set (match_operand:VI12_AVX512VL 0 "register_operand")
(vec_merge:VI12_AVX512VL
(plusminus:VI12_AVX512VL
@ -11519,7 +11519,7 @@
"TARGET_AVX512BW"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<plusminus_insn><mode>3"
(define_insn "*<insn><mode>3"
[(set (match_operand:VI_AVX2 0 "register_operand" "=x,v")
(plusminus:VI_AVX2
(match_operand:VI_AVX2 1 "bcst_vector_operand" "<comm>0,v")
@ -11534,7 +11534,7 @@
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*<plusminus_insn><mode>3_mask"
(define_insn "*<insn><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL
(plusminus:VI48_AVX512VL
@ -11548,7 +11548,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*<plusminus_insn><mode>3_mask"
(define_insn "*<insn><mode>3_mask"
[(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI12_AVX512VL
(plusminus:VI12_AVX512VL
@ -11562,7 +11562,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<sse2_avx2>_<plusminus_insn><mode>3<mask_name>"
(define_expand "<sse2_avx2>_<insn><mode>3<mask_name>"
[(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand")
(sat_plusminus:VI12_AVX2_AVX512BW
(match_operand:VI12_AVX2_AVX512BW 1 "vector_operand")
@ -11570,7 +11570,7 @@
"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<sse2_avx2>_<plusminus_insn><mode>3<mask_name>"
(define_insn "*<sse2_avx2>_<insn><mode>3<mask_name>"
[(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand" "=x,v")
(sat_plusminus:VI12_AVX2_AVX512BW
(match_operand:VI12_AVX2_AVX512BW 1 "vector_operand" "<comm>0,v")
@ -12316,7 +12316,7 @@
(const_string "0")))
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<mask_codefor><shift_insn><mode>3<mask_name>"
(define_insn "<mask_codefor><insn><mode>3<mask_name>"
[(set (match_operand:VI248_AVX512BW_2 0 "register_operand" "=v,v")
(any_lshift:VI248_AVX512BW_2
(match_operand:VI248_AVX512BW_2 1 "nonimmediate_operand" "v,vm")
@ -12330,7 +12330,7 @@
(const_string "0")))
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<shift_insn><mode>3"
(define_insn "<insn><mode>3"
[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
(any_lshift:VI248_AVX2
(match_operand:VI248_AVX2 1 "register_operand" "0,x")
@ -12349,7 +12349,7 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<shift_insn><mode>3<mask_name>"
(define_insn "<insn><mode>3<mask_name>"
[(set (match_operand:VI248_AVX512BW 0 "register_operand" "=v,v")
(any_lshift:VI248_AVX512BW
(match_operand:VI248_AVX512BW 1 "nonimmediate_operand" "v,m")
@ -12390,7 +12390,7 @@
operands[4] = gen_lowpart (<MODE>mode, operands[3]);
})
(define_insn "avx512bw_<shift_insn><mode>3"
(define_insn "avx512bw_<insn><mode>3"
[(set (match_operand:VIMAX_AVX512VL 0 "register_operand" "=v")
(any_lshift:VIMAX_AVX512VL
(match_operand:VIMAX_AVX512VL 1 "nonimmediate_operand" "vm")
@ -12405,7 +12405,7 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<sse2_avx2>_<shift_insn><mode>3"
(define_insn "<sse2_avx2>_<insn><mode>3"
[(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,v")
(any_lshift:VIMAX_AVX2
(match_operand:VIMAX_AVX2 1 "register_operand" "0,v")
@ -17611,7 +17611,7 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
(define_expand "<optab>v16qiv16hi2"
(define_expand "<insn>v16qiv16hi2"
[(set (match_operand:V16HI 0 "register_operand")
(any_extend:V16HI
(match_operand:V16QI 1 "nonimmediate_operand")))]
@ -17628,7 +17628,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
(define_expand "<optab>v32qiv32hi2"
(define_expand "<insn>v32qiv32hi2"
[(set (match_operand:V32HI 0 "register_operand")
(any_extend:V32HI
(match_operand:V32QI 1 "nonimmediate_operand")))]
@ -17683,7 +17683,7 @@
(any_extend:V8HI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
(define_expand "<optab>v8qiv8hi2"
(define_expand "<insn>v8qiv8hi2"
[(set (match_operand:V8HI 0 "register_operand")
(any_extend:V8HI
(match_operand:V8QI 1 "nonimmediate_operand")))]
@ -17707,7 +17707,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
(define_expand "<optab>v16qiv16si2"
(define_expand "<insn>v16qiv16si2"
[(set (match_operand:V16SI 0 "register_operand")
(any_extend:V16SI
(match_operand:V16QI 1 "nonimmediate_operand")))]
@ -17760,7 +17760,7 @@
(any_extend:V8SI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
(define_expand "<optab>v8qiv8si2"
(define_expand "<insn>v8qiv8si2"
[(set (match_operand:V8SI 0 "register_operand")
(any_extend:V8SI
(match_operand:V8QI 1 "nonimmediate_operand")))]
@ -17823,7 +17823,7 @@
(any_extend:V4SI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V4QImode, 0);")
(define_expand "<optab>v4qiv4si2"
(define_expand "<insn>v4qiv4si2"
[(set (match_operand:V4SI 0 "register_operand")
(any_extend:V4SI
(match_operand:V4QI 1 "nonimmediate_operand")))]
@ -17847,7 +17847,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
(define_expand "<optab>v16hiv16si2"
(define_expand "<insn>v16hiv16si2"
[(set (match_operand:V16SI 0 "register_operand")
(any_extend:V16SI
(match_operand:V16HI 1 "nonimmediate_operand")))]
@ -17864,7 +17864,7 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
(define_expand "<optab>v8hiv8si2"
(define_expand "<insn>v8hiv8si2"
[(set (match_operand:V8SI 0 "register_operand")
(any_extend:V8SI
(match_operand:V8HI 1 "nonimmediate_operand")))]
@ -17915,7 +17915,7 @@
(any_extend:V4SI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V4HImode, 0);")
(define_expand "<optab>v4hiv4si2"
(define_expand "<insn>v4hiv4si2"
[(set (match_operand:V4SI 0 "register_operand")
(any_extend:V4SI
(match_operand:V4HI 1 "nonimmediate_operand")))]
@ -17973,7 +17973,7 @@
(any_extend:V8DI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
(define_expand "<optab>v8qiv8di2"
(define_expand "<insn>v8qiv8di2"
[(set (match_operand:V8DI 0 "register_operand")
(any_extend:V8DI
(match_operand:V8QI 1 "nonimmediate_operand")))]
@ -18034,7 +18034,7 @@
(any_extend:V4DI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V4QImode, 0);")
(define_expand "<optab>v4qiv4di2"
(define_expand "<insn>v4qiv4di2"
[(set (match_operand:V4DI 0 "register_operand")
(any_extend:V4DI
(match_operand:V4QI 1 "nonimmediate_operand")))]
@ -18062,7 +18062,7 @@
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
(define_expand "<optab>v2qiv2di2"
(define_expand "<insn>v2qiv2di2"
[(set (match_operand:V2DI 0 "register_operand")
(any_extend:V2DI
(match_operand:V2QI 1 "register_operand")))]
@ -18083,7 +18083,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
(define_expand "<optab>v8hiv8di2"
(define_expand "<insn>v8hiv8di2"
[(set (match_operand:V8DI 0 "register_operand")
(any_extend:V8DI
(match_operand:V8HI 1 "nonimmediate_operand")))]
@ -18132,7 +18132,7 @@
(any_extend:V4DI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V4HImode, 0);")
(define_expand "<optab>v4hiv4di2"
(define_expand "<insn>v4hiv4di2"
[(set (match_operand:V4DI 0 "register_operand")
(any_extend:V4DI
(match_operand:V4HI 1 "nonimmediate_operand")))]
@ -18193,7 +18193,7 @@
(any_extend:V2DI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V2HImode, 0);")
(define_expand "<optab>v2hiv2di2"
(define_expand "<insn>v2hiv2di2"
[(set (match_operand:V2DI 0 "register_operand")
(any_extend:V2DI
(match_operand:V2HI 1 "nonimmediate_operand")))]
@ -18217,7 +18217,7 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
(define_expand "<optab>v8siv8di2"
(define_expand "<insn>v8siv8di2"
[(set (match_operand:V8DI 0 "register_operand" "=v")
(any_extend:V8DI
(match_operand:V8SI 1 "nonimmediate_operand" "vm")))]
@ -18234,7 +18234,7 @@
(set_attr "prefix_extra" "1")
(set_attr "mode" "OI")])
(define_expand "<optab>v4siv4di2"
(define_expand "<insn>v4siv4di2"
[(set (match_operand:V4DI 0 "register_operand" "=v")
(any_extend:V4DI
(match_operand:V4SI 1 "nonimmediate_operand" "vm")))]
@ -18283,7 +18283,7 @@
(any_extend:V2DI (match_dup 1)))]
"operands[1] = adjust_address_nv (operands[1], V2SImode, 0);")
(define_expand "<optab>v2siv2di2"
(define_expand "<insn>v2siv2di2"
[(set (match_operand:V2DI 0 "register_operand")
(any_extend:V2DI
(match_operand:V2SI 1 "nonimmediate_operand")))]
@ -19822,7 +19822,7 @@
(set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_expand "<shift_insn><mode>3"
(define_expand "<insn><mode>3"
[(set (match_operand:VI1_AVX512 0 "register_operand")
(any_shift:VI1_AVX512
(match_operand:VI1_AVX512 1 "register_operand")
@ -21575,7 +21575,7 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<avx2_avx512>_<shift_insn>v<mode><mask_name>"
(define_insn "<avx2_avx512>_<insn>v<mode><mask_name>"
[(set (match_operand:VI48_AVX512F 0 "register_operand" "=v")
(any_lshift:VI48_AVX512F
(match_operand:VI48_AVX512F 1 "register_operand" "v")
@ -21586,7 +21586,7 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<avx2_avx512>_<shift_insn>v<mode><mask_name>"
(define_insn "<avx2_avx512>_<insn>v<mode><mask_name>"
[(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v")
(any_lshift:VI2_AVX512VL
(match_operand:VI2_AVX512VL 1 "register_operand" "v")