*** empty log message ***
From-SVN: r1145
This commit is contained in:
Richard Kenner
parent
8f80f94287
commit
c803cac305
@ -69,6 +69,14 @@
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(const_string "yes")
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(const_string "no")))
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;; Attribute to indicate if an instruction is 'safe' to fill a load
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;; delay slot because the first real instruction geneated is something
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;; like load of $1 or a clobbered register. Logical operations (&, |, ^)
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;; which have operand[2] being a large integer constant fall into
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;; this category.
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(define_attr "safe" "no,yes" (const_string "no"))
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;; Attribute describing the processor. This attribute must match exactly
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;; with the processor_type enumeration in mips.h.
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@ -1153,19 +1161,98 @@ move\\t%0,%z4\\n\\
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;; the optimizer can fold things together, at the expense of not moving the
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;; constant out of loops.
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d,?d,?d")
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(define_expand "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(and:SI (match_operand:SI 1 "arith32_operand" "dKIM")
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(match_operand:SI 2 "arith32_operand" "dKIM")))]
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""
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"
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{
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extern rtx gen_andsi3_internal2 ();
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/* Canonlicalize */
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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rtx temp;
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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emit_move_insn (operands[0],
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gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) & INTVAL (operands[2])));
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DONE;
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}
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temp = operands[1];
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operands[1] = operands[2];
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operands[2] = temp;
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}
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if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
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{
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emit_insn (gen_andsi3_internal2 (operands[0],
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operands[1],
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operands[2],
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gen_reg_rtx (SImode)));
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DONE;
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}
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}")
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(define_insn "andsi3_internal1"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(and:SI (match_operand:SI 1 "arith32_operand" "%d,d")
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(match_operand:SI 2 "arith32_operand" "d,K")))]
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""
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"@
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and\\t%0,%1,%2
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andi\\t%0,%1,%x2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "1")])
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(define_insn "andsi3_internal2"
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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(and:SI (match_operand:SI 1 "arith32_operand" "%d,d,d,d")
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))]
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))
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(clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
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""
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"@
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and\\t%0,%1,%2
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andi\\t%0,%1,%x2
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%[li\\t%@,%X2\;and\\t%0,%1,%@%]
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%[li\\t%@,%X2\;and\\t%0,%1,%@%]"
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lui\\t%3,(%X2)>>16\;and\\t%0,%1,%3
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li\\t%@,%X2\;and\\t%0,%1,%@"
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[(set_attr "type" "arith,arith,multi,multi")
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(set_attr "mode" "SI")
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(set_attr "length" "1,1,2,3")])
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(set_attr "length" "1,1,2,3")
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(set_attr "safe" "no,no,yes,yes")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(and:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "lui_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 2))
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(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
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"")
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(and:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "large_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
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(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
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"
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{
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int val = INTVAL (operands[2]);
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operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
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operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
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}")
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(define_insn "anddi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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@ -1190,19 +1277,98 @@ move\\t%0,%z4\\n\\
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(set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
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"")
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(define_insn "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d,?d,?d")
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(define_expand "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ior:SI (match_operand:SI 1 "arith32_operand" "dKIM")
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(match_operand:SI 2 "arith32_operand" "dKIM")))]
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""
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"
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{
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extern rtx gen_iorsi3_internal2 ();
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/* Canonlicalize */
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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rtx temp;
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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emit_move_insn (operands[0],
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gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) | INTVAL (operands[2])));
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DONE;
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}
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temp = operands[1];
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operands[1] = operands[2];
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operands[2] = temp;
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}
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if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
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{
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emit_insn (gen_iorsi3_internal2 (operands[0],
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operands[1],
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operands[2],
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gen_reg_rtx (SImode)));
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DONE;
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}
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}")
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(define_insn "iorsi3_internal1"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(ior:SI (match_operand:SI 1 "arith32_operand" "%d,d")
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(match_operand:SI 2 "arith32_operand" "d,K")))]
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""
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"@
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or\\t%0,%1,%2
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ori\\t%0,%1,%x2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "1")])
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(define_insn "iorsi3_internal2"
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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(ior:SI (match_operand:SI 1 "arith32_operand" "%d,d,d,d")
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))]
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))
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(clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
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""
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"@
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or\\t%0,%1,%2
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ori\\t%0,%1,%x2
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%[li\\t%@,%X2\;or\\t%0,%1,%@%]
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%[li\\t%@,%X2\;or\\t%0,%1,%@%]"
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lui\\t%3,(%X2)>>16\;or\\t%0,%1,%3
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li\\t%@,%X2\;or\\t%0,%1,%@"
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[(set_attr "type" "arith,arith,multi,multi")
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(set_attr "mode" "SI")
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(set_attr "length" "1,1,2,3")])
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(set_attr "length" "1,1,2,3")
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(set_attr "safe" "no,no,yes,yes")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(ior:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "lui_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 2))
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(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
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"")
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(ior:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "large_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
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(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
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"
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{
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int val = INTVAL (operands[2]);
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operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
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operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
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}")
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(define_insn "iordi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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@ -1227,19 +1393,99 @@ move\\t%0,%z4\\n\\
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(set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
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"")
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d,?d,?d")
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(define_expand "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(xor:SI (match_operand:SI 1 "arith32_operand" "dKIM")
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(match_operand:SI 2 "arith32_operand" "dKIM")))]
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""
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"
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{
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extern rtx gen_xorsi3_internal2 ();
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/* Canonlicalize */
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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rtx temp;
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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emit_move_insn (operands[0],
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gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) ^ INTVAL (operands[2])));
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DONE;
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}
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temp = operands[1];
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operands[1] = operands[2];
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operands[2] = temp;
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}
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if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
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{
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emit_insn (gen_xorsi3_internal2 (operands[0],
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operands[1],
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operands[2],
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gen_reg_rtx (SImode)));
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DONE;
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}
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}")
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(define_insn "xorsi3_internal1"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(xor:SI (match_operand:SI 1 "arith32_operand" "%d,d")
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(match_operand:SI 2 "arith32_operand" "d,K")))]
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""
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"@
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xor\\t%0,%1,%2
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xori\\t%0,%1,%x2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "1")])
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(define_insn "xorsi3_internal2"
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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(xor:SI (match_operand:SI 1 "arith32_operand" "%d,d,d,d")
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))]
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(match_operand:SI 2 "arith32_operand" "d,K,I,M")))
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(clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
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""
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"@
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xor\\t%0,%1,%2
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xori\\t%0,%1,%x2
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%[li\\t%@,%X2\;xor\\t%0,%1,%@%]
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%[li\\t%@,%X2\;xor\\t%0,%1,%@%]"
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lui\\t%3,(%X2)>>16\;xor\\t%0,%1,%3
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li\\t%@,%X2\;xor\\t%0,%1,%@"
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[(set_attr "type" "arith,arith,multi,multi")
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(set_attr "mode" "SI")
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(set_attr "length" "1,1,2,3")])
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(set_attr "length" "1,1,2,3")
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(set_attr "safe" "no,no,yes,yes")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "lui_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 2))
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(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
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"")
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "large_int" "")))
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(clobber (match_operand:SI 3 "register_operand" ""))]
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"reload_completed && !TARGET_DEBUG_D_MODE"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
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(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
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"
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{
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int val = INTVAL (operands[2]);
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operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
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operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
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}")
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(define_insn "xordi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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