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(divsi3, udivsi3, modsi3, umodsi3): Simplify.

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(ashlsi3): Clean up indentation and commentary.

From-SVN: r9541
This commit is contained in:
Torbjorn Granlund 1995-04-29 10:06:54 +00:00
parent 1c1f2d29a0
commit c210e6aeae
1 changed files with 15 additions and 77 deletions
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92
gcc/config/pa/pa.md
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@ -2587,30 +2587,14 @@
"" ""
" "
{ {
operands[3] = gen_reg_rtx(SImode); operands[3] = gen_reg_rtx (SImode);
if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 0))) if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
{ DONE;
emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
emit
(gen_rtx
(PARALLEL, VOIDmode,
gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
gen_rtx (DIV, SImode,
gen_rtx (REG, SImode, 26),
gen_rtx (REG, SImode, 25))),
gen_rtx (CLOBBER, VOIDmode, operands[3]),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
}
DONE;
}") }")
(define_insn "" (define_insn ""
[(set (reg:SI 29) [(set (reg:SI 29)
(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a")) (clobber (match_operand:SI 1 "register_operand" "=a"))
(clobber (reg:SI 26)) (clobber (reg:SI 26))
(clobber (reg:SI 25)) (clobber (reg:SI 25))
@ -2639,30 +2623,14 @@
"" ""
" "
{ {
operands[3] = gen_reg_rtx(SImode); operands[3] = gen_reg_rtx (SImode);
if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 1))) if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
{ DONE;
emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
emit
(gen_rtx
(PARALLEL, VOIDmode,
gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
gen_rtx (UDIV, SImode,
gen_rtx (REG, SImode, 26),
gen_rtx (REG, SImode, 25))),
gen_rtx (CLOBBER, VOIDmode, operands[3]),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
}
DONE;
}") }")
(define_insn "" (define_insn ""
[(set (reg:SI 29) [(set (reg:SI 29)
(udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a")) (clobber (match_operand:SI 1 "register_operand" "=a"))
(clobber (reg:SI 26)) (clobber (reg:SI 26))
(clobber (reg:SI 25)) (clobber (reg:SI 25))
@ -2691,22 +2659,7 @@
"" ""
" "
{ {
operands[3] = gen_reg_rtx(SImode); operands[3] = gen_reg_rtx (SImode);
emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
emit
(gen_rtx
(PARALLEL, VOIDmode,
gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
gen_rtx (MOD, SImode,
gen_rtx (REG, SImode, 26),
gen_rtx (REG, SImode, 25))),
gen_rtx (CLOBBER, VOIDmode, operands[3]),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
DONE;
}") }")
(define_insn "" (define_insn ""
@ -2739,22 +2692,7 @@
"" ""
" "
{ {
operands[3] = gen_reg_rtx(SImode); operands[3] = gen_reg_rtx (SImode);
emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
emit
(gen_rtx
(PARALLEL, VOIDmode,
gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
gen_rtx (UMOD, SImode,
gen_rtx (REG, SImode, 26),
gen_rtx (REG, SImode, 25))),
gen_rtx (CLOBBER, VOIDmode, operands[3]),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
DONE;
}") }")
(define_insn "" (define_insn ""
@ -3142,14 +3080,14 @@
{ {
rtx temp = gen_reg_rtx (SImode); rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2])); emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
if (GET_CODE (operands[1]) == CONST_INT) if (GET_CODE (operands[1]) == CONST_INT)
emit_insn (gen_zvdep_imm (operands[0], operands[1], temp)); emit_insn (gen_zvdep_imm (operands[0], operands[1], temp));
else else
emit_insn (gen_zvdep32 (operands[0], operands[1], temp)); emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
DONE; DONE;
} }
/* Make sure both inputs are not constants, /* Make sure both inputs are not constants,
the recognizer can't handle that. */ there are no patterns for that. */
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
}") }")