alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode value in paradoxical SImode result...
* alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode value in paradoxical SImode result, rather than truncating midpoint. From-SVN: r23655
This commit is contained in:
parent
9d1a7ce0cc
commit
bd8dc16507
@ -1,3 +1,8 @@
|
||||
Sat Nov 14 15:05:07 1998 Richard Henderson <rth@cygnus.com>
|
||||
|
||||
* alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode
|
||||
value in paradoxical SImode result, rather than truncating midpoint.
|
||||
|
||||
Fri Nov 13 22:19:23 1998 Richard Henderson <rth@cygnus.com>
|
||||
|
||||
* alpha.c (reg_not_elim_operand): New.
|
||||
|
@ -427,19 +427,22 @@
|
||||
""
|
||||
"
|
||||
{
|
||||
rtx op1 = gen_lowpart (DImode, operands[1]);
|
||||
rtx op2 = gen_lowpart (DImode, operands[2]);
|
||||
|
||||
if (! cse_not_expected)
|
||||
if (optimize)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_adddi3 (tmp, op1, op2));
|
||||
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
|
||||
rtx op1 = gen_lowpart (DImode, operands[1]);
|
||||
rtx op2 = gen_lowpart (DImode, operands[2]);
|
||||
|
||||
if (! cse_not_expected)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_adddi3 (tmp, op1, op2));
|
||||
emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
|
||||
}
|
||||
else
|
||||
emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
|
||||
DONE;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
|
||||
DONE;
|
||||
} ")
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
||||
@ -719,18 +722,21 @@
|
||||
""
|
||||
"
|
||||
{
|
||||
rtx op1 = gen_lowpart (DImode, operands[1]);
|
||||
rtx op2 = gen_lowpart (DImode, operands[2]);
|
||||
|
||||
if (! cse_not_expected)
|
||||
if (optimize)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_subdi3 (tmp, op1, op2));
|
||||
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
|
||||
rtx op1 = gen_lowpart (DImode, operands[1]);
|
||||
rtx op2 = gen_lowpart (DImode, operands[2]);
|
||||
|
||||
if (! cse_not_expected)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_subdi3 (tmp, op1, op2));
|
||||
emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
|
||||
}
|
||||
else
|
||||
emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
|
||||
DONE;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
|
||||
DONE;
|
||||
} ")
|
||||
|
||||
(define_insn ""
|
||||
|
Loading…
Reference in New Issue
Block a user