MatCat.OpenSource/8sa1-gcc
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

combine.c (nonzero_bits): For paradoxical subregs, take LOAD_EXTENDED_OP into account.

Browse Source 
* combine.c (nonzero_bits): For paradoxical subregs, take
	LOAD_EXTENDED_OP into account.

From-SVN: r19928
This commit is contained in:
J"orn Rennecke 1998-05-21 11:35:10 +00:00 committed by Joern Rennecke
parent d4dfe7d66c
commit b52ce03da5
2 changed files with 21 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gcc/ChangeLog
View File

@ -1,3 +1,8 @@
Thu May 21 19:32:27 1998 J"orn Rennecke <amylaar@cygnus.co.uk>
* combine.c (nonzero_bits): For paradoxical subregs, take
LOAD_EXTENDED_OP into account.
Thu May 21 11:51:15 1998 Dave Brolley <brolley@cygnus.com>
* configure.in (extra_c_objs): add prefix.o.

24
gcc/combine.c
View File

@ -7693,15 +7693,23 @@ nonzero_bits (x, mode)
{
nonzero &= nonzero_bits (SUBREG_REG (x), mode);
#ifndef WORD_REGISTER_OPERATIONS
/* On many CISC machines, accessing an object in a wider mode
causes the high-order bits to become undefined. So they are
not known to be zero. */
if (GET_MODE_SIZE (GET_MODE (x))
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
nonzero |= (GET_MODE_MASK (GET_MODE (x))
& ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
? (nonzero
& (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
: LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
#endif
{
/* On many CISC machines, accessing an object in a wider mode
causes the high-order bits to become undefined. So they are
not known to be zero. */
if (GET_MODE_SIZE (GET_MODE (x))
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
nonzero |= (GET_MODE_MASK (GET_MODE (x))
& ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
}
}
break;