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(sqrtsf2, sqrtdf2): Change POWERPCSQR to PPCFPX.

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(maxsf3, minsf3, maxdf3, mindf3): New patterns using fsel instruction.

From-SVN: r6385
This commit is contained in:
Richard Kenner 1994-01-12 06:02:09 -05:00
parent 6a7ec0a773
commit 8e871c0596
1 changed files with 189 additions and 5 deletions
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194
gcc/config/rs6000/rs6000.md
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@ -1,6 +1,6 @@
;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
;; Copyright (C) 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@nyu.edu)
;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GNU CC.
@ -2262,13 +2262,13 @@
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_POWERPCSQR || TARGET_POWER2"
"TARGET_PPCFPX || TARGET_POWER2"
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPCSQR"
"TARGET_PPCFPX"
"fsqrts %0,%1"
[(set_attr "type" "ssqrt")])
@ -2279,6 +2279,98 @@
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
;; instruction and some auxiliary computations. Then we just have a single
;; DEFINE_INSN for fsel and the define_splits to make them if made by
;; combine.
(define_expand "maxsf3"
[(set (match_dup 3)
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(if_then_else:SF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (SFmode); }")
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "reg_or_short_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
"TARGET_PPCFPX"
[(set (match_dup 3)
(minus:SF (match_dup 1) (match_dup 2)))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(if_then_else:SF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"")
(define_expand "minsf3"
[(set (match_dup 3)
(minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
(match_operand:SF 1 "gpc_reg_operand" "")))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(if_then_else:SF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (SFmode); }")
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "reg_or_short_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
"TARGET_PPCFPX"
[(set (match_dup 3)
(minus:SF (match_dup 2) (match_dup 1)))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(if_then_else:SF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_PPCFPX"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f"))
(const_int 0)))
(clobber (match_scratch:SF 4 "=f"))]
"TARGET_PPCFPX"
"fsel. %4,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
(compare:CCFP
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f"))
(const_int 0)))
(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(if_then_else:SF (ge (match_dup 1) (const_int 0))
(match_dup 2)
(match_dup 3)))]
"TARGET_PPCFPX"
"fsel. %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
@ -2371,9 +2463,101 @@
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPCSQR || TARGET_POWER2"
"TARGET_PPCFPX || TARGET_POWER2"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
;; instruction and some auxiliary computations. Then we just have a single
;; DEFINE_INSN for fsel and the define_splits to make them if made by
;; combine.
(define_expand "maxdf3"
[(set (match_dup 3)
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(if_then_else:DF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "reg_or_short_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
"TARGET_PPCFPX"
[(set (match_dup 3)
(minus:DF (match_dup 1) (match_dup 2)))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(if_then_else:DF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"")
(define_expand "mindf3"
[(set (match_dup 3)
(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
(match_operand:DF 1 "gpc_reg_operand" "")))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(if_then_else:DF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "reg_or_short_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
"TARGET_PPCFPX"
[(set (match_dup 3)
(minus:DF (match_dup 2) (match_dup 1)))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(if_then_else:DF (ge (match_dup 3)
(const_int 0))
(match_dup 1)
(match_dup 2)))]
"")
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:DF 2 "gpc_reg_operand" "f")
(match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_PPCFPX"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:DF 2 "gpc_reg_operand" "f")
(match_operand:DF 3 "gpc_reg_operand" "f"))
(const_int 0)))
(clobber (match_scratch:DF 4 "=f"))]
"TARGET_PPCFPX"
"fsel. %4,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
(compare:CCFP
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
(const_int 0))
(match_operand:DF 2 "gpc_reg_operand" "f")
(match_operand:DF 3 "gpc_reg_operand" "f"))
(const_int 0)))
(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_dup 1) (const_int 0))
(match_dup 2)
(match_dup 3)))]
"TARGET_PPCFPX"
"fsel. %0,%1,%2,%3"
[(set_attr "type" "fp")])
;; Conversions to and from floating-point.
(define_expand "floatsidf2"