(zero_extendsidi2): New pattern.
(extendqidi2, extendhidi2, extendsidi2, extendplussidi): New patterns. (adddia_sexthishl32, adddid_sexthishl32): New patterns. (adddi_dilshr32, adddi_dishl32, adddi_mem): New patterns. (adddi3, subdi3): Allow more alternatives. (subdia_sexthishl32, subdid_sexthishl32): New patterns. (subdi_dishl32, subdi_mem): New patterns. (negdi2): New pattern. (ashldi_sexthi, ashldi_const32, ashldi_const, ashldi3): New patterns. (subreg1ashrdi_const32, ashrdi_const32): New patterns. (ashrdi_const32_mem, ashrdi_const, ashrdi3): New patterns. (subreg1lshrdi_const32, lshrdi_const32, lshrdi_const, lshrdi3): Ditto. (lshrsi_31): New pattern. (lshrsi_16, lshrsi_17_24): New names for old unnamed patterns. From-SVN: r8753
This commit is contained in:
Richard Kenner
parent
f1d947250e
commit
801aee461f
@ -1368,6 +1368,28 @@
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;; zero extension instructions
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;; this one is the canonical form for (lshiftrt:DI x 32)
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(define_insn "zero_extendsidi2"
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[(set (match_operand:DI 0 "general_operand" "ro,<,>")
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(zero_extend:DI (match_operand:SI 1 "general_operand" "rm,rm,rm")))]
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""
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"*
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{
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CC_STATUS_INIT;
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if (which_alternative == 2)
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return \"clr%.l %0\;move%.l %1,%0\";
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if (which_alternative == 1)
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return \"move%.l %1,%0\;clr%.l %0\";
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if (GET_CODE (operands[0]) == REG)
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else
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operands[2] = adj_offsettable_operand (operands[0], 4);
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if (ADDRESS_REG_P (operands[0]))
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return \"move%.l %1,%2\;sub%.l %0,%0\";
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else
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return \"move%.l %1,%2\;clr%.l %0\";
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}")
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(const_int 0))
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@ -1543,6 +1565,78 @@
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;; sign extension instructions
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(define_insn "extendqidi2"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI
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(match_operand:QI 1 "general_operand" "rm")))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (TARGET_68020)
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return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
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else
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return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
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}")
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(define_insn "extendhidi2"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI
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(match_operand:HI 1 "general_operand" "rm")))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (TARGET_68020)
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return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
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else
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return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
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}")
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(define_insn "extendsidi2"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI
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(match_operand:SI 1 "general_operand" "rm")))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (TARGET_68020)
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return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
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else
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return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
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}")
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;; Special case when one can avoid register clobbering, copy and test
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;; Maybe there is a way to make that the general case, by forcing the
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;; result of the SI tree to be in the lower register of the DI target
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(define_insn "extendplussidi"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
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(match_operand:SI 2 "general_operand" "rmn"))))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (GET_CODE (operands[1]) == CONST_INT
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&& (unsigned) INTVAL (operands[1]) > 8)
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{
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rtx tmp = operands[1];
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operands[1] = operands[2];
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operands[2] = tmp;
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}
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if (TARGET_68020)
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return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;extb%.l %0\";
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else
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return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;ext%.w %0\;ext%.l %0\";
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}")
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(define_insn "extendhisi2"
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[(set (match_operand:SI 0 "general_operand" "=*d,a")
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(sign_extend:SI
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@ -1839,16 +1933,104 @@
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;; add instructions
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(plus:DI (match_operand:DI 1 "register_operand" "%0")
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(match_operand:DI 2 "register_operand" "d")))]
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(define_insn "adddia_sexthishl32"
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[(set (match_operand:DI 0 "register_operand" "+a")
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(plus:DI (ashift:DI (sign_extend:DI
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(match_operand:HI 1 "general_operand" "rm"))
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(const_int 32))
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(match_dup 0)))]
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""
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"*
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{
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CC_STATUS_INIT;
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return \"add%.w %1,%0\";
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} ")
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(define_insn "adddid_sexthishl32"
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[(set (match_operand:DI 0 "register_operand" "+do")
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(plus:DI (ashift:DI (sign_extend:DI
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(match_operand:HI 1 "general_operand" "rm"))
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(const_int 32))
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(match_dup 0)))
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(clobber (match_scratch:SI 2 "=a"))]
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""
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"*
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{
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CC_STATUS_INIT;
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return \"move%.w %1,%2\;add%.l %2,%0\";
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} ")
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(define_insn "adddi_dilshr32"
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[(set (match_operand:DI 0 "general_operand" "=ro")
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(plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
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(const_int 32))
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(match_operand:DI 2 "general_operand" "0")))]
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""
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"*
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[0]) == REG)
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operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else
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operands[0] = adj_offsettable_operand (operands[0], 4);
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return \"add%.l %1,%0\";
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} ")
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(define_insn "adddi_dishl32"
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[(set (match_operand:DI 0 "general_operand" "=ro")
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(plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
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(const_int 32))
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(match_operand:DI 2 "general_operand" "0")))]
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""
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"*
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[1]) == REG)
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else
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operands[1] = adj_offsettable_operand (operands[1], 4);
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return \"add%.l %1,%0\";
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} ")
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(define_insn "adddi_mem"
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[(set (match_operand:DI 0 "general_operand" "=m")
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(plus:DI (match_operand:DI 1 "general_operand" "%0")
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(match_operand:DI 2 "general_operand" "d")))
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(clobber (match_scratch:SI 3 "=d"))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[1] = adj_offsettable_operand (operands[0], 4);
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operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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return \"add%.l %4,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
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} ")
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
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(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
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(match_operand:DI 2 "general_operand" "ao,>,d,<")))]
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""
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"*
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{
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if (which_alternative == 3)
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return \"add%.l %2,%0\;addx%.l %2,%0\";
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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return \"add%.l %3,%1\;addx%.l %2,%0\";
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if (which_alternative == 1)
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{
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CC_STATUS_INIT;
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return \"add%.l %2,%0\;add%.l %2,%1\;negx%.l %0\;neg%.l %0\";
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}
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if (GET_CODE (operands[2]) == REG)
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[3] = adj_offsettable_operand (operands[2], 4);
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if (which_alternative == 2)
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return \"add%.l %3,%1\;addx%.l %2,%0\";
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CC_STATUS_INIT;
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/* negx + neg simulates (non-existent) addx #0 */
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/* TODO : this should work also for CONST operands[2] */
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return \"add%.l %3,%1\;negx%.l %0\;neg%.l %0\;add%.l %2,%0\";
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} ")
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;; Note that the middle two alternatives are near-duplicates
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@ -2271,16 +2453,83 @@
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;; subtract instructions
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "register_operand" "d")))]
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(define_insn "subdia_sexthishl32"
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[(set (match_operand:DI 0 "register_operand" "+a")
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(minus:DI (match_dup 0)
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(ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
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(const_int 32))))]
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""
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"*
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{
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CC_STATUS_INIT;
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return \"sub%.w %1,%0\";
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} ")
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(define_insn "subdid_sexthishl32"
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[(set (match_operand:DI 0 "register_operand" "+do")
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(minus:DI (match_dup 0)
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(ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
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(const_int 32))))
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(clobber (match_scratch:SI 2 "=a"))]
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""
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"*
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{
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CC_STATUS_INIT;
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return \"move%.w %1,%2\;sub%.l %2,%0\";
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} ")
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(define_insn "subdi_dishl32"
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[(set (match_operand:DI 0 "register_operand" "+d")
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(minus:DI (match_dup 0)
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(ashift:DI (match_operand:DI 1 "register_operand" "d")
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(const_int 32))))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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return \"sub%.l %1,%0\";
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} ")
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(define_insn "subdi_mem"
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[(set (match_operand:DI 0 "general_operand" "=m")
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(minus:DI (match_operand:DI 1 "general_operand" "0")
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(match_operand:DI 2 "general_operand" "d")))
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(clobber (match_scratch:SI 3 "=d"))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[1] = adj_offsettable_operand (operands[0], 4);
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operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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return \"sub%.l %4,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
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} ")
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
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(minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
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(match_operand:DI 2 "general_operand" "ao,>,d,<")))]
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""
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"*
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{
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if (which_alternative == 3)
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return \"sub%.l %2,%0\;subx%.l %2,%0\";
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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return \"sub%.l %3,%1\;subx%.l %2,%0\";
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if (which_alternative == 1)
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{
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CC_STATUS_INIT;
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return \"neg%.l %0\;add%.l %2,%0\;sub%.l %2,%1\;negx%.l %0\";
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}
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if (GET_CODE (operands[2]) == REG)
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[3] = adj_offsettable_operand (operands[2], 4);
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if (which_alternative == 2)
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return \"sub%.l %3,%1\;subx%.l %2,%0\";
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CC_STATUS_INIT;
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/* neg + negx simulates (non-existent) subx #0 */
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/* TODO : this should work also for CONST operands[2] */
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return \"neg%.l %0\;sub%.l %3,%1\;negx%.l %0\;sub%.l %2,%0\";
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} ")
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(define_insn "subsi3"
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@ -3311,6 +3560,24 @@
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;; negation instructions
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(define_insn "negdi2"
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[(set (match_operand:DI 0 "general_operand" "=d*ao,<")
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(neg:DI (match_operand:DI 1 "general_operand" "0,0")))]
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""
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"*
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{
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if (which_alternative == 1)
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return \"neg%.l %0\;negx%.l %0\";
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if (GET_CODE (operands[0]) == REG)
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else
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operands[1] = adj_offsettable_operand (operands[0], 4);
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if (ADDRESS_REG_P (operands[0]))
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return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
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else
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return \"neg%.l %1\;negx%.l %0\";
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} ")
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "general_operand" "=dm")
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(neg:SI (match_operand:SI 1 "general_operand" "0")))]
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@ -3607,6 +3874,77 @@
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;; arithmetic shift instructions
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;; We don't need the shift memory by 1 bit instruction
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(define_insn "ashldi_sexthi"
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[(set (match_operand:DI 0 "general_operand" "=*da")
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(ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
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(const_int 32)))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (DATA_REG_P (operands[0]))
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return \"move%.w %1,%0\;ext%.l %0\;clr%.l %2\";
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else
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return \"move%.w %1,%0\;sub%.l %2,%2\";
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} ")
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(define_insn "ashldi_const32"
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[(set (match_operand:DI 0 "general_operand" "=ro,<,>")
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(ashift:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
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(const_int 32)))]
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""
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"*
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[1]) == REG)
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else
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operands[3] = adj_offsettable_operand (operands[1], 4);
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if (which_alternative == 1)
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return \"clr%.l %0\;move%.l %3,%0\";
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if (which_alternative == 2)
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return \"move%.l %3,%0\;clr%.l %0\";
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if (GET_CODE (operands[0]) == REG)
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else
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operands[2] = adj_offsettable_operand (operands[0], 4);
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if (ADDRESS_REG_P (operands[2]))
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return \"move%.l %3,%0\;sub%.l %2,%2\";
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else
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return \"move%.l %3,%0\;clr%.l %2\";
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} ")
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(define_insn "ashldi_const"
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[(set (match_operand:DI 0 "general_operand" "=d")
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(ashift:DI (match_operand:DI 1 "general_operand" "0")
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(match_operand 2 "const_int_operand" "n")))]
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"(INTVAL (operands[2]) == 1
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|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
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"*
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{
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
|
||||
if (INTVAL (operands[2]) == 1)
|
||||
return \"add%.l %1,%1\;addx%.l %0,%0\";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
|
||||
else/* if (INTVAL (operands[2]) == 3)*/
|
||||
return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
|
||||
} ")
|
||||
|
||||
(define_expand "ashldi3"
|
||||
[(set (match_operand:DI 0 "general_operand" "=rm")
|
||||
(ashift:DI (match_operand:DI 1 "general_operand" "rm")
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) != CONST_INT
|
||||
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
|
||||
&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
|
||||
FAIL;
|
||||
} ")
|
||||
|
||||
;; On all 68k models, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
@ -3699,6 +4037,81 @@
|
||||
return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
|
||||
}")
|
||||
|
||||
(define_insn "subreg1ashrdi_const32"
|
||||
[(set (match_operand:SI 0 "general_operand" "=rm")
|
||||
(subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
|
||||
(const_int 32)) 1))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
return \"move%.l %1,%0\";
|
||||
} ")
|
||||
|
||||
(define_insn "ashrdi_const32"
|
||||
[(set (match_operand:DI 0 "general_operand" "=d")
|
||||
(ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
|
||||
(const_int 32)))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
|
||||
if (TARGET_68020)
|
||||
return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
|
||||
else
|
||||
return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
|
||||
} ")
|
||||
|
||||
(define_insn "ashrdi_const32_mem"
|
||||
[(set (match_operand:DI 0 "general_operand" "=o,<")
|
||||
(ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
|
||||
(const_int 32)))
|
||||
(clobber (match_scratch:SI 2 "=d,d"))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
if (which_alternative == 1)
|
||||
operands[3] = operands[0];
|
||||
else
|
||||
operands[3] = adj_offsettable_operand (operands[0], 4);
|
||||
if (TARGET_68020)
|
||||
return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
|
||||
else
|
||||
return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
|
||||
} ")
|
||||
|
||||
(define_insn "ashrdi_const"
|
||||
[(set (match_operand:DI 0 "general_operand" "=d")
|
||||
(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
"(INTVAL (operands[2]) == 1
|
||||
|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
|
||||
"*
|
||||
{
|
||||
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
|
||||
CC_STATUS_INIT;
|
||||
if (INTVAL (operands[2]) == 1)
|
||||
return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
else/* if (INTVAL (operands[2]) == 3)*/
|
||||
return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
} ")
|
||||
|
||||
(define_expand "ashrdi3"
|
||||
[(set (match_operand:DI 0 "general_operand" "=rm")
|
||||
(ashiftrt:DI (match_operand:DI 1 "general_operand" "rm")
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) != CONST_INT
|
||||
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
|
||||
&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
|
||||
FAIL;
|
||||
} ")
|
||||
|
||||
(define_insn "ashrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
@ -3736,10 +4149,92 @@
|
||||
|
||||
;; logical shift instructions
|
||||
|
||||
(define_insn "subreg1lshrdi_const32"
|
||||
[(set (match_operand:SI 0 "general_operand" "=rm")
|
||||
(subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
|
||||
(const_int 32)) 1))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
return \"move%.l %1,%0\";
|
||||
} ")
|
||||
|
||||
(define_insn "lshrdi_const32"
|
||||
[(set (match_operand:DI 0 "general_operand" "=ro,<,>")
|
||||
(lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
|
||||
(const_int 32)))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
if (which_alternative == 1)
|
||||
return \"move%.l %1,%0\;clr%.l %0\";
|
||||
if (which_alternative == 2)
|
||||
return \"clr%.l %0\;move%.l %1,%0\";
|
||||
if (GET_CODE (operands[0]) == REG)
|
||||
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
|
||||
else
|
||||
operands[2] = adj_offsettable_operand (operands[0], 4);
|
||||
if (GET_CODE (operands[1]) == REG)
|
||||
operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
|
||||
else
|
||||
operands[3] = adj_offsettable_operand (operands[1], 4);
|
||||
if (ADDRESS_REG_P (operands[0]))
|
||||
return \"move%.l %1,%2\;sub%.l %0,%0\";
|
||||
else
|
||||
return \"move%.l %1,%2\;clr%.l %0\";
|
||||
} ")
|
||||
|
||||
(define_insn "lshrdi_const"
|
||||
[(set (match_operand:DI 0 "general_operand" "=d")
|
||||
(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
"(INTVAL (operands[2]) == 1
|
||||
|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
|
||||
if (INTVAL (operands[2]) == 1)
|
||||
return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
else /*if (INTVAL (operands[2]) == 3)*/
|
||||
return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
|
||||
} ")
|
||||
|
||||
(define_expand "lshrdi3"
|
||||
[(set (match_operand:DI 0 "general_operand" "=rm")
|
||||
(lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
|
||||
(match_operand 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) != CONST_INT
|
||||
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
|
||||
&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
|
||||
FAIL;
|
||||
} ")
|
||||
|
||||
;; On all 68k models, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
(define_insn "lshrsi_31"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(const_int 31)))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
#if defined(MOTOROLA) && !defined(CRDS)
|
||||
return \"roxl%.l %#1,%0\;moveq%.l %#0,%d0\;roxl%.l %#1,%0\";
|
||||
#else
|
||||
return \"roxl%.l %#1,%0\;moveq %#0,%d0\;roxl%.l %#1,%0\";
|
||||
#endif
|
||||
}")
|
||||
|
||||
;; On all 68k models, this makes faster code in a special case.
|
||||
|
||||
(define_insn "lshrsi_16"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(const_int 16)))]
|
||||
@ -3752,7 +4247,7 @@
|
||||
|
||||
;; On the 68000, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
(define_insn "lshrsi_17_24"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "const_int_operand" "n")))]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user