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arm: Fix mult autovectorization patterm for iwmmxt (PR target/99786)

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Similarly to other recently-added autovectorization patterns, mult has
been erroneously enabled for iwmmxt. However, V4HI and V2SI modes are
supported, so we make an exception for them.

The new testcase is derived from gcc.dg/ubsan/pr79904.c, with
additional modes added.

I kept dg-do compile because 'assemble' results in error messages from
the assembler, which are not related to this PR:

Error: selected processor does not support `tmcrr wr0,r4,r5' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr2,.L5' in ARM mode
Error: selected processor does not support `wmulul wr0,wr0,wr2' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr2,.L8' in ARM mode
Error: selected processor does not support `wmulwl wr0,wr0,wr2' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode

2021-03-29  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/99786

	gcc/
	* config/arm/vec-common.md (mul<mode>3): Disable on iwMMXT, expect
	for V4HI and V2SI.

	gcc/testsuite/
	* gcc.target/arm/pr99786.c: New test.
This commit is contained in:
Christophe Lyon 2021-03-29 12:41:08 +00:00
parent bf24f4ec73
commit 7c1d6e8999
2 changed files with 34 additions and 1 deletions
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5
gcc/config/arm/vec-common.md
View File

@ -103,7 +103,10 @@
[(set (match_operand:VDQWH 0 "s_register_operand") [(set (match_operand:VDQWH 0 "s_register_operand")
(mult:VDQWH (match_operand:VDQWH 1 "s_register_operand") (mult:VDQWH (match_operand:VDQWH 1 "s_register_operand")
(match_operand:VDQWH 2 "s_register_operand")))] (match_operand:VDQWH 2 "s_register_operand")))]
"ARM_HAVE_<MODE>_ARITH" "ARM_HAVE_<MODE>_ARITH
&& (!TARGET_REALLY_IWMMXT
|| <MODE>mode == V4HImode
|| <MODE>mode == V2SImode)"
) )
(define_expand "smin<mode>3" (define_expand "smin<mode>3"

30
gcc/testsuite/gcc.target/arm/pr99786.c Normal file
View File

@ -0,0 +1,30 @@
/* { dg-do compile } */
/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
/* { dg-require-effective-target arm32 } */
/* { dg-require-effective-target arm_iwmmxt_ok } */
/* { dg-options "-O3 -mcpu=iwmmxt" } */
typedef signed char V __attribute__((vector_size (8)));
void
foo (V *a)
{
*a = *a * 3;
}
typedef signed short Vshort __attribute__((vector_size (8)));
void
foo_short (Vshort *a)
{
*a = *a * 3;
}
typedef signed int Vint __attribute__((vector_size (8)));
void
foo_int (Vint *a)
{
*a = *a * 3;
}