aarch64: Simplify LSE cas generation
The cas insn is a single insn, and if expanded properly need not be split after reload. Use the proper inputs for the insn. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Force oldval into the rval register for TARGET_LSE; emit the compare during initial expansion so that it may be deleted if unused. (aarch64_gen_atomic_cas): Remove. * config/aarch64/atomics.md (@aarch64_compare_and_swap<SHORT>_lse): Change =&r to +r for operand 0; use match_dup for operand 2; remove is_weak and mod_f operands as unused. Drop the split and merge with... (@aarch64_atomic_cas<SHORT>): ... this pattern's output; remove. (@aarch64_compare_and_swap<GPI>_lse): Similarly. (@aarch64_atomic_cas<GPI>): Similarly. From-SVN: r265656
This commit is contained in:
Richard Henderson
Richard Henderson
parent
187cea947e
commit
77f33f44ba
@ -1,3 +1,17 @@
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2018-10-31 Richard Henderson <richard.henderson@linaro.org>
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* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
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Force oldval into the rval register for TARGET_LSE; emit the compare
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during initial expansion so that it may be deleted if unused.
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(aarch64_gen_atomic_cas): Remove.
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* config/aarch64/atomics.md (@aarch64_compare_and_swap<SHORT>_lse):
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Change =&r to +r for operand 0; use match_dup for operand 2;
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remove is_weak and mod_f operands as unused. Drop the split
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and merge with...
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(@aarch64_atomic_cas<SHORT>): ... this pattern's output; remove.
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(@aarch64_compare_and_swap<GPI>_lse): Similarly.
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(@aarch64_atomic_cas<GPI>): Similarly.
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2018-10-31 Richard Biener <rguenther@suse.de>
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* tree-eh.c (replace_trapping_overflow): Simplify ABS_EXPR case
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@ -563,7 +563,6 @@ rtx aarch64_load_tp (rtx);
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void aarch64_expand_compare_and_swap (rtx op[]);
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void aarch64_split_compare_and_swap (rtx op[]);
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void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
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bool aarch64_atomic_ldop_supported_p (enum rtx_code);
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void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
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@ -14620,16 +14620,27 @@ aarch64_expand_compare_and_swap (rtx operands[])
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}
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if (TARGET_LSE)
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emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem, oldval,
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newval, is_weak, mod_s,
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mod_f));
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{
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/* The CAS insn requires oldval and rval overlap, but we need to
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have a copy of oldval saved across the operation to tell if
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the operation is successful. */
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if (mode == QImode || mode == HImode)
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rval = copy_to_mode_reg (SImode, gen_lowpart (SImode, oldval));
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else if (reg_overlap_mentioned_p (rval, oldval))
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rval = copy_to_mode_reg (mode, oldval);
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else
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emit_move_insn (rval, oldval);
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emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem,
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newval, mod_s));
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aarch64_gen_compare_reg (EQ, rval, oldval);
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}
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else
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emit_insn (gen_aarch64_compare_and_swap (mode, rval, mem, oldval, newval,
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is_weak, mod_s, mod_f));
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if (mode == QImode || mode == HImode)
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emit_move_insn (operands[1], gen_lowpart (mode, rval));
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rval = gen_lowpart (mode, rval);
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emit_move_insn (operands[1], rval);
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x = gen_rtx_REG (CCmode, CC_REGNUM);
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x = gen_rtx_EQ (SImode, x, const0_rtx);
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@ -14679,31 +14690,6 @@ aarch64_emit_post_barrier (enum memmodel model)
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}
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}
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/* Emit an atomic compare-and-swap operation. RVAL is the destination register
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for the data in memory. EXPECTED is the value expected to be in memory.
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DESIRED is the value to store to memory. MEM is the memory location. MODEL
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is the memory ordering to use. */
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void
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aarch64_gen_atomic_cas (rtx rval, rtx mem,
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rtx expected, rtx desired,
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rtx model)
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{
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machine_mode mode;
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mode = GET_MODE (mem);
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/* Move the expected value into the CAS destination register. */
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emit_insn (gen_rtx_SET (rval, expected));
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/* Emit the CAS. */
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emit_insn (gen_aarch64_atomic_cas (mode, rval, mem, desired, model));
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/* Compare the expected value with the value loaded by the CAS, to establish
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whether the swap was made. */
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aarch64_gen_compare_reg (EQ, rval, expected);
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}
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/* Split a compare and swap pattern. */
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void
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@ -85,56 +85,50 @@
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}
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)
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(define_insn_and_split "@aarch64_compare_and_swap<mode>_lse"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(define_insn "@aarch64_compare_and_swap<mode>_lse"
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[(set (match_operand:SI 0 "register_operand" "+r") ;; val out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(set (match_dup 1)
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(unspec_volatile:SHORT
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[(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected
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(match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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[(match_dup 0) ;; expected
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(match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 3 "const_int_operand")] ;; mod_s
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UNSPECV_ATOMIC_CMPSW))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_cas (operands[0], operands[1],
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operands[2], operands[3],
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operands[5]);
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DONE;
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}
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)
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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(define_insn_and_split "@aarch64_compare_and_swap<mode>_lse"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:GPI 0 "register_operand" "=&r") ;; val out
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(define_insn "@aarch64_compare_and_swap<mode>_lse"
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[(set (match_operand:GPI 0 "register_operand" "+r") ;; val out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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[(match_dup 0) ;; expected
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(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 3 "const_int_operand")] ;; mod_s
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UNSPECV_ATOMIC_CMPSW))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_cas (operands[0], operands[1],
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operands[2], operands[3],
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operands[5]);
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DONE;
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}
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)
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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(define_expand "atomic_exchange<mode>"
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[(match_operand:ALLI 0 "register_operand" "")
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@ -610,55 +604,6 @@
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return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
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})
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;; Atomic compare-and-swap: HI and smaller modes.
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(define_insn "@aarch64_atomic_cas<mode>"
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[(set (match_operand:SI 0 "register_operand" "+&r") ;; out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory.
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(set (match_dup 1)
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(unspec_volatile:SHORT
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[(match_dup 0)
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(match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ") ;; value.
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(match_operand:SI 3 "const_int_operand" "")] ;; model.
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UNSPECV_ATOMIC_CAS))]
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"TARGET_LSE && reload_completed"
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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;; Atomic compare-and-swap: SI and larger modes.
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(define_insn "@aarch64_atomic_cas<mode>"
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[(set (match_operand:GPI 0 "register_operand" "+&r") ;; out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory.
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_dup 0)
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(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") ;; value.
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(match_operand:SI 3 "const_int_operand" "")] ;; model.
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UNSPECV_ATOMIC_CAS))]
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"TARGET_LSE && reload_completed"
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
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else if (is_mm_release (model))
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return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
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else
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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;; Atomic load-op: Load data, operate, store result, keep data.
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(define_insn "@aarch64_atomic_load<atomic_ldop><mode>"
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