Merge push patterns for memory/nonmemory
From-SVN: r8048
This commit is contained in:
Michael Meissner
parent
68dab18d53
commit
6ecbf3001a
@ -1064,15 +1064,15 @@
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""
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"
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{
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/* Special case memory->memory moves */
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/* Special case memory->memory moves and pushes */
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if (TARGET_MOVE
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&& (reload_in_progress | reload_completed) == 0
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[1]) == MEM)
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&& (GET_CODE (operands[1]) == MEM || push_operand (operands[0], SFmode)))
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{
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rtx (*genfunc) PROTO((rtx, rtx));
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if (push_operand (operands[0], SFmode))
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genfunc = (TARGET_386) ? gen_movsf_push386 : gen_movsf_push486_mem;
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genfunc = (TARGET_386) ? gen_movsf_push386 : gen_movsf_push486;
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else
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genfunc = gen_movsf_mem;
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@ -1110,8 +1110,9 @@
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}")
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(define_insn "movsf_push486"
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[(set (match_operand:SF 0 "push_operand" "=<,<")
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(match_operand:SF 1 "nonmemory_operand" "rF,f"))]
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[(set (match_operand:SF 0 "push_operand" "=<,<,<")
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(match_operand:SF 1 "general_operand" "rF,f,m"))
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(clobber (match_scratch:SI 2 "=X,X,r"))]
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"!TARGET_386"
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"*
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{
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@ -1134,18 +1135,15 @@
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output_asm_insn (AS1 (fst%S0,%0), xops);
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RET;
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}
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return AS1 (push%L1,%1);
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}")
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(define_insn "movsf_push486_mem"
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[(set (match_operand:SF 0 "push_operand" "=<")
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(match_operand:SF 1 "memory_operand" "m"))
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(clobber (match_scratch:SI 2 "=r"))]
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"!TARGET_386"
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"*
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{
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output_asm_insn (AS2 (mov%L2,%1,%2), operands);
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return AS1 (push%L2,%2);
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else if (GET_CODE (operands[1]) != MEM)
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return AS1 (push%L1,%1);
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else
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{
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output_asm_insn (AS2 (mov%L2,%1,%2), operands);
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return AS1 (push%L2,%2);
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}
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}")
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;; Special memory<->memory pattern that combine will recreate from the
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@ -1237,15 +1235,15 @@
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""
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"
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{
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/* Special case memory->memory moves */
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/* Special case memory->memory moves and pushes */
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if (TARGET_MOVE
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&& (reload_in_progress | reload_completed) == 0
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[1]) == MEM)
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&& (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DFmode)))
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{
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rtx (*genfunc) PROTO((rtx, rtx));
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if (push_operand (operands[0], DFmode))
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genfunc = (TARGET_386) ? gen_movdf_push386 : gen_movdf_push486_mem;
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genfunc = (TARGET_386) ? gen_movdf_push386 : gen_movdf_push486;
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else
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genfunc = gen_movdf_mem;
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@ -1282,8 +1280,10 @@
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}")
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(define_insn "movdf_push486"
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[(set (match_operand:DF 0 "push_operand" "=<,<")
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(match_operand:DF 1 "nonmemory_operand" "rF,f"))]
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[(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
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(match_operand:DF 1 "general_operand" "rF,f,o,o"))
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(clobber (match_scratch:SI 2 "=X,X,&r,&r"))
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(clobber (match_scratch:SI 3 "=X,X,&r,X"))]
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"!TARGET_386"
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"*
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{
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@ -1304,42 +1304,37 @@
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RET;
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}
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else
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else if (GET_CODE (operands[1]) != MEM)
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return output_move_double (operands);
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}")
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(define_insn "movdf_push486_mem"
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[(set (match_operand:DF 0 "push_operand" "=<,<")
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(match_operand:DF 1 "general_operand" "o,o"))
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(clobber (match_scratch:SI 2 "=&r,&r"))
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(clobber (match_scratch:SI 3 "=&r,X"))]
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"!TARGET_386"
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"*
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{
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rtx low[1], high[1], xop[4];
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split_di (&operands[1], 1, low, high);
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = high[0];
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xop[3] = low[0];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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{
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rtx low[1], high[1], xop[4];
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RET;
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split_di (&operands[1], 1, low, high);
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = high[0];
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xop[3] = low[0];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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RET;
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}
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}")
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(define_insn "movdf_mem"
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@ -1453,15 +1448,15 @@
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""
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"
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{
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/* Special case memory->memory moves */
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/* Special case memory->memory moves and pushes */
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if (TARGET_MOVE
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&& (reload_in_progress | reload_completed) == 0
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[1]) == MEM)
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&& (GET_CODE (operands[1]) == MEM || push_operand (operands[0], XFmode)))
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{
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rtx (*genfunc) PROTO((rtx, rtx));
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if (push_operand (operands[0], XFmode))
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genfunc = (TARGET_386) ? gen_movxf_push386 : gen_movxf_push486_mem;
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genfunc = (TARGET_386) ? gen_movxf_push386 : gen_movxf_push486;
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else
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genfunc = gen_movxf_mem;
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@ -1496,8 +1491,10 @@
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}")
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(define_insn "movxf_push486"
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[(set (match_operand:XF 0 "push_operand" "=<,<")
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(match_operand:XF 1 "nonmemory_operand" "rF,f"))]
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[(set (match_operand:XF 0 "push_operand" "=<,<,<,<")
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(match_operand:XF 1 "general_operand" "rF,f,o,o"))
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(clobber (match_scratch:SI 2 "=X,X,&r,&r"))
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(clobber (match_scratch:SI 3 "=X,X,&r,X"))]
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"!TARGET_386"
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"*
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{
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@ -1516,46 +1513,41 @@
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RET;
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}
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else
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else if (GET_CODE (operands[1]) != MEM)
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return output_move_double (operands);
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}")
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(define_insn "movxf_push486_mem"
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[(set (match_operand:XF 0 "push_operand" "=<,<")
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(match_operand:XF 1 "memory_operand" "o,o"))
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(clobber (match_scratch:SI 2 "=&r,&r"))
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(clobber (match_scratch:SI 3 "=&r,X"))]
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"!TARGET_386"
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"*
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{
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rtx xop[5];
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = adj_offsettable_operand (operands[1], 8);
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xop[3] = adj_offsettable_operand (operands[1], 4);
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xop[4] = operands[1];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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output_asm_insn (AS2 (mov%L0,%4,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%4,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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{
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rtx xop[5];
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RET;
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = adj_offsettable_operand (operands[1], 8);
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xop[3] = adj_offsettable_operand (operands[1], 4);
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xop[4] = operands[1];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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output_asm_insn (AS2 (mov%L0,%4,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%4,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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RET;
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}
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}")
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(define_insn "movxf_mem"
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@ -1675,15 +1667,15 @@
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""
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"
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{
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/* Special case memory->memory moves */
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/* Special case memory->memory moves and pushes */
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if (TARGET_MOVE
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&& (reload_in_progress | reload_completed) == 0
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[1]) == MEM)
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&& (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DImode)))
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{
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rtx (*genfunc) PROTO((rtx, rtx));
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if (push_operand (operands[0], DImode))
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genfunc = (TARGET_386) ? gen_movdi_push386 : gen_movdi_push486_mem;
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genfunc = (TARGET_386) ? gen_movdi_push386 : gen_movdi_push486;
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else
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genfunc = gen_movdi_mem;
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@ -1699,43 +1691,43 @@
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"* return output_move_double (operands);")
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(define_insn "movdi_push486"
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[(set (match_operand:DI 0 "push_operand" "=<")
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(match_operand:DI 1 "nonmemory_operand" "riF"))]
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"!TARGET_386"
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"* return output_move_double (operands);")
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(define_insn "movdi_push486_mem"
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[(set (match_operand:DI 0 "push_operand" "=<,<")
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(match_operand:DI 1 "memory_operand" "o,o"))
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(clobber (match_scratch:SI 2 "=&r,=&r"))
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(clobber (match_scratch:SI 3 "=&r,X"))]
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[(set (match_operand:DI 0 "push_operand" "=<,<,<")
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(match_operand:DI 1 "general_operand" "riF,o,o"))
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(clobber (match_scratch:SI 2 "=X,&r,=&r"))
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(clobber (match_scratch:SI 3 "=X,&r,X"))]
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"!TARGET_386"
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"*
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{
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rtx low[1], high[1], xop[4];
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if (GET_CODE (operands[1]) != MEM)
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return output_move_double (operands);
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split_di (&operands[1], 1, low, high);
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = high[0];
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xop[3] = low[0];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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{
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rtx low[1], high[1], xop[4];
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RET;
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split_di (&operands[1], 1, low, high);
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xop[0] = operands[2];
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xop[1] = operands[3];
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xop[2] = high[0];
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xop[3] = low[0];
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if (GET_CODE (operands[3]) == REG)
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{ /* 2 scratch registers available */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%1), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS1 (push%L0,%1), xop);
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}
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else
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{ /* 1 scratch register */
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output_asm_insn (AS2 (mov%L0,%2,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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output_asm_insn (AS2 (mov%L0,%3,%0), xop);
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output_asm_insn (AS1 (push%L0,%0), xop);
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}
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RET;
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}
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}")
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(define_insn "movdi_mem"
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