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From-SVN: r10887
This commit is contained in:
Michael Meissner 1995-12-27 22:22:24 +00:00
parent ca12b8a431
commit 4c0c634c64
3 changed files with 16 additions and 23 deletions
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22
gcc/config/rs6000/rs6000.c
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@ -467,8 +467,10 @@ gpc_reg3_operand (op, mode)
register rtx op;
enum machine_mode mode;
{
return (register_operand (op, mode)
&& (GET_CODE (op) != REG || REGNO (op) == 3 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
if (GET_CODE (op) != REG || mode != GET_MODE (op))
return 0; /* do not allow SUBREG's */
return (REGNO (op) == 3 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
}
/* Returns 1 if OP is register 4 or is a pseudo register. */
@ -478,20 +480,10 @@ gpc_reg4_operand (op, mode)
register rtx op;
enum machine_mode mode;
{
return (register_operand (op, mode)
&& (GET_CODE (op) != REG || REGNO (op) == 4 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
}
if (GET_CODE (op) != REG || mode != GET_MODE (op))
return 0; /* do not allow SUBREG's */
/* Returns 1 if OP is register 3 or 4 or is a pseudo register. */
int
gpc_reg34_operand (op, mode)
register rtx op;
enum machine_mode mode;
{
return (register_operand (op, mode)
&& (GET_CODE (op) != REG || REGNO (op) == 3 || REGNO (op) == 4
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
return (REGNO (op) == 4 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
}
/* Returns 1 if OP is either a pseudo-register or CR1. */

2
gcc/config/rs6000/rs6000.h
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@ -2600,7 +2600,6 @@ do { \
{"gpc_reg0_operand", {SUBREG, REG}}, \
{"gpc_reg3_operand", {SUBREG, REG}}, \
{"gpc_reg4_operand", {SUBREG, REG}}, \
{"gpc_reg34_operand", {SUBREG, REG}}, \
{"cc_reg0_operand", {SUBREG, REG}}, \
{"cc_reg1_operand", {SUBREG, REG}}, \
{"cc_reg_operand", {SUBREG, REG}}, \
@ -2656,7 +2655,6 @@ extern int non_short_cint_operand ();
extern int gpc_reg0_operand ();
extern int gpc_reg3_operand ();
extern int gpc_reg4_operand ();
extern int gpc_reg34_operand ();
extern int gpc_reg_operand ();
extern int cc_reg0_operand ();
extern int cc_reg1_operand ();

15
gcc/config/rs6000/rs6000.md
View File

@ -3672,7 +3672,10 @@
{
if (! TARGET_POWER && ! TARGET_POWERPC)
{
emit_insn (gen_mulsidi3_common (operands[0], operands[1], operands[2]));
emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
emit_insn (gen_mulsidi3_common ());
emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
DONE;
}
else if (TARGET_POWER)
@ -3683,11 +3686,11 @@
}")
(define_insn "mulsidi3_common"
[(set (match_operand:DI 0 "gpc_reg3_operand" "=w")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg3_operand" "%u"))
(sign_extend:DI (match_operand:SI 2 "gpc_reg4_operand" "v"))))
(clobber (match_scratch:SI 3 "=l"))
(clobber (match_scratch:SI 4 "=z"))]
[(set (reg:DI 3)
(mult:DI (sign_extend:DI (reg:SI 3))
(sign_extend:DI (reg:SI 4))))
(clobber (match_scratch:SI 0 "=l"))
(clobber (match_scratch:SI 1 "=z"))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mull"
[(set_attr "type" "jmpreg")])