pa.md (zero extension patterns): Turn into a define_expand and define_insn pair.
* pa/pa.md (zero extension patterns): Turn into a define_expand and define_insn pair. From-SVN: r13670
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@ -2648,34 +2648,59 @@
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;;- zero extension instructions
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;; We have define_expand for zero extension patterns to make sure the
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;; operands get loaded into registers. The define_insns accept
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;; memory operands. This gives us better overall code than just
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;; having a pattern that does or does not accept memory operands.
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(define_insn "zero_extendhisi2"
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI
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(match_operand:HI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(zero_extend:SI
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(match_operand:HI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
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""
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(match_operand:HI 1 "move_operand" "r,RQ")))]
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"GET_CODE (operands[1]) != CONST_INT"
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"@
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extru %1,31,16,%0
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ldh%M1 %1,%0"
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[(set_attr "type" "shift,load")
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(set_attr "length" "4,4")])
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(define_insn "zero_extendqihi2"
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(define_expand "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI
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(match_operand:QI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(zero_extend:HI
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(match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
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""
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(match_operand:QI 1 "move_operand" "r,RQ")))]
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"GET_CODE (operands[1]) != CONST_INT"
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"@
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extru %1,31,8,%0
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ldb%M1 %1,%0"
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[(set_attr "type" "shift,load")
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(set_attr "length" "4,4")])
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(define_insn "zero_extendqisi2"
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(define_expand "zero_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI
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(match_operand:QI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(zero_extend:SI
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(match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
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""
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(match_operand:QI 1 "move_operand" "r,RQ")))]
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"GET_CODE (operands[1]) != CONST_INT"
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"@
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extru %1,31,8,%0
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ldb%M1 %1,%0"
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