aarch64: Add support for unpacked SVE conditional BIC
This patch adds support for unpacked conditional BIC. The type suffix could be taken from the element size or the container size, so the patch continues to use the element size. This is consistent with the existing support for unconditional BIC. gcc/ * config/aarch64/aarch64-sve.md (*cond_bic<mode>_2): Extend from SVE_FULL_I to SVE_I. (*cond_bic<mode>_any): Likewise. gcc/testsuite/ * g++.target/aarch64/sve/cond_bic_1.C: New test. * g++.target/aarch64/sve/cond_bic_2.C: Likewise. * g++.target/aarch64/sve/cond_bic_3.C: Likewise. * g++.target/aarch64/sve/cond_bic_4.C: Likewise.
This commit is contained in:
Richard Sandiford
parent
7446de5a2a
commit
37426e0f06
@ -4475,13 +4475,13 @@
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;; Predicated integer BIC, merging with the first input.
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(define_insn "*cond_bic<mode>_2"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(and:SVE_FULL_I
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w"))
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(and:SVE_I
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(not:SVE_I
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(match_operand:SVE_I 2 "register_operand" "0, w"))
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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@ -4493,14 +4493,14 @@
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;; Predicated integer BIC, merging with an independent value.
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(define_insn_and_rewrite "*cond_bic<mode>_any"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(and:SVE_FULL_I
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w, w, w"))
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w, w, w"))
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(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, 0, w")]
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(and:SVE_I
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(not:SVE_I
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(match_operand:SVE_I 3 "register_operand" "w, w, w, w"))
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(match_operand:SVE_I 2 "register_operand" "0, w, w, w"))
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(match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, 0, w")]
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UNSPEC_SEL))]
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"TARGET_SVE && !rtx_equal_p (operands[2], operands[4])"
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"@
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40
gcc/testsuite/g++.target/aarch64/sve/cond_bic_1.C
Normal file
40
gcc/testsuite/g++.target/aarch64/sve/cond_bic_1.C
Normal file
@ -0,0 +1,40 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? a & ~b : a; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tbic\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, \1\.s\n} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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31
gcc/testsuite/g++.target/aarch64/sve/cond_bic_2.C
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31
gcc/testsuite/g++.target/aarch64/sve/cond_bic_2.C
Normal file
@ -0,0 +1,31 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? a & ~b : b; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */
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36
gcc/testsuite/g++.target/aarch64/sve/cond_bic_3.C
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36
gcc/testsuite/g++.target/aarch64/sve/cond_bic_3.C
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@ -0,0 +1,36 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? a & ~b : c; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tbic\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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36
gcc/testsuite/g++.target/aarch64/sve/cond_bic_4.C
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36
gcc/testsuite/g++.target/aarch64/sve/cond_bic_4.C
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@ -0,0 +1,36 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? a & ~b : 0; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tbic\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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