entered into RCS
From-SVN: r3872
This commit is contained in:
Richard Stallman
parent
5aac39057b
commit
3615587a37
@ -186,10 +186,13 @@ extern int target_flags;
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On the clipper, 0-15 hold int, 16-31 hold float. */
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On the clipper, 0-15 hold int, 16-31 hold float. DImode regs must be
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even */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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((GET_MODE_CLASS(MODE) == MODE_FLOAT) ? (REGNO) >= 16 : (REGNO) < 16)
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((GET_MODE_CLASS(MODE) == MODE_FLOAT) \
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? (REGNO) >= 16 \
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: (REGNO) < 16 && ((MODE) !=DImode || ((REGNO) & 1) == 0))
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/* Value is 1 if it is a good idea to tie two pseudo registers
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when one has mode MODE1 and one has mode MODE2.
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@ -206,7 +206,9 @@
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}
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return \"stord %1,%0\"; /* f-> m */
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}")
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}"
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[(set_attr "type" "store,store")
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(set_attr "cc" "clobber,unchanged")])
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(define_expand "movsf"
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@ -278,7 +280,8 @@
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return \"stors %1,%0\"; /* f-> m */
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return \"storw %1,%0\"; /* r -> m */
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}")
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}"
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[(set_attr "type" "store")])
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(define_expand "movdi"
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@ -389,6 +392,10 @@
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if (which_alternative == 2)
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{
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val = INTVAL (operands[1]); /* known const ->reg */
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if (val == -1)
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return \"notq $0,%0\";
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if (val < 0 || val >= 16)
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return \"loadi %1,%0\";
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@ -478,6 +485,7 @@
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"storb %1,%0"
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[(set_attr "type" "store")])
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;;
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;; block move
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;;
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@ -624,7 +632,7 @@
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""
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"cnvwd %1,%0")
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;; Float-to-fix conversion insns.
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(define_insn "fix_truncsfsi2"
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@ -646,7 +654,8 @@
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(plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
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(match_operand:DF 2 "fp_reg_operand" "f")))]
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""
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"addd %2,%0")
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"addd %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "addsf3"
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@ -654,7 +663,8 @@
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(plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
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(match_operand:SF 2 "fp_reg_operand" "f")))]
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""
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"adds %2,%0")
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"adds %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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@ -678,16 +688,12 @@
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
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(plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
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(match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
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(match_operand:SI 2 "nonmemory_operand" "rn,0,r")))]
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""
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"*
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{
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if (which_alternative == 2) /* 3 address version */
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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return \"loada %a2(%1),%0\";
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return \"loada [%2](%1),%0\";
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}
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return \"loada [%2](%1),%0\";
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/* 2 address version */
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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@ -772,14 +778,16 @@
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(minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
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(match_operand:DF 2 "fp_reg_operand" "f")))]
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""
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"subd %2,%0")
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"subd %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "subsf3"
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[(set (match_operand:SF 0 "fp_reg_operand" "=f")
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(minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
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(match_operand:SF 2 "fp_reg_operand" "f")))]
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""
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"subs %2,%0")
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"subs %2,%0"
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[(set_attr "type" "fp")])
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;;- Multiply instructions.
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@ -789,14 +797,34 @@
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(mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
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(match_operand:DF 2 "fp_reg_operand" "f")))]
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""
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"muld %2,%0")
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"muld %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "mulsf3"
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[(set (match_operand:SF 0 "fp_reg_operand" "=f")
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(mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
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(match_operand:SF 2 "fp_reg_operand" "f")))]
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""
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"muls %2,%0")
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"muls %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "mulsidi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
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(sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
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""
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"mulwx %2,%0"
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[(set_attr "type" "arith")
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(set_attr "cc" "clobber")])
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(define_insn "umulsidi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
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(zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
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""
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"mulwux %2,%0"
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[(set_attr "type" "arith")
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(set_attr "cc" "clobber")])
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r")
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@ -807,7 +835,6 @@
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[(set_attr "type" "arith")
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(set_attr "cc" "clobber")])
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;;- Divide and mod instructions.
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@ -816,14 +843,16 @@
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(div:DF (match_operand:DF 1 "fp_reg_operand" "0")
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(match_operand:DF 2 "fp_reg_operand" "f")))]
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""
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"divd %2,%0")
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"divd %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "divsf3"
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[(set (match_operand:SF 0 "fp_reg_operand" "=f")
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(div:SF (match_operand:SF 1 "fp_reg_operand" "0")
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(match_operand:SF 2 "fp_reg_operand" "f")))]
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""
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"divs %2,%0")
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"divs %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "divsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r")
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@ -899,13 +928,15 @@
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[(set (match_operand:DF 0 "fp_reg_operand" "=f")
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(neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
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""
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"negd %1,%0")
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"negd %1,%0"
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[(set_attr "type" "fp")])
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(define_insn "negsf2"
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[(set (match_operand:SF 0 "fp_reg_operand" "=f")
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(neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
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""
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"negs %1,%0")
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"negs %1,%0"
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[(set_attr "type" "fp")])
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "int_reg_operand" "=r")
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@ -928,6 +959,33 @@
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;; then emitting a right shift with the shift count negated. This means
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;; that all actual shift counts in the RTL will be positive.
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(define_expand "ashrdi3"
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[(set (match_operand:DI 0 "int_reg_operand" "")
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(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT)
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operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
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}")
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
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(match_operand:SI 2 "const_int_operand" "n")))]
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""
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"shali $%n2,%0"
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[(set_attr "type" "arith")])
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
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(neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
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""
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"shal %2,%0"
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[(set_attr "type" "arith")])
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(define_expand "ashrsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "")
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(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
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@ -955,6 +1013,21 @@
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"shaw %2,%0"
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[(set_attr "type" "arith")])
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;;
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;; left shift
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;;
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(define_insn "ashldi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r,r")
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(ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n")))]
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""
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"@
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shal %2,%0
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shali %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "ashlsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r,r")
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(ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
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@ -979,6 +1052,36 @@
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}"
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[(set_attr "type" "arith")])
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;;
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;; logical shift
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;;
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(define_expand "lshrdi3"
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[(set (match_operand:DI 0 "int_reg_operand" "")
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(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT)
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operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
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}")
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
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(match_operand:SI 2 "const_int_operand" "n")))]
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""
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"shlli $%n2,%0"
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[(set_attr "type" "arith")])
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
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(neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
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""
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"shll %2,%0"
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[(set_attr "type" "arith")])
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(define_expand "lshrsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "")
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@ -1007,6 +1110,16 @@
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"shlw %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "lshldi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r,r")
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(lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n")))]
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""
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"@
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shll %2,%0
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shlli %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "lshlsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r,r")
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(lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
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@ -1017,7 +1130,36 @@
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shli %2,%0"
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[(set_attr "type" "arith")])
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;; rotate
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;;
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;; rotate insn
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;;
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(define_expand "rotrdi3"
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[(set (match_operand:DI 0 "int_reg_operand" "")
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(rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT)
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operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
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}")
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
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(match_operand:SI 2 "const_int_operand" "n")))]
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""
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"rotli $%n2,%0"
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[(set_attr "type" "arith")])
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(define_insn ""
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[(set (match_operand:DI 0 "int_reg_operand" "=r")
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(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
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(neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
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""
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"rotl %2,%0"
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[(set_attr "type" "arith")])
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(define_expand "rotrsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "")
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(rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
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@ -1045,6 +1187,16 @@
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"rotw %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "rotldi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r,r")
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(rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n")))]
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""
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"@
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rotl %2,%0
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rotli %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "rotlsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r,r")
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(rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
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@ -1056,6 +1208,9 @@
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[(set_attr "type" "arith")])
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;;
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;; jump and branch insns
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;;
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(define_insn "jump"
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[(set (pc)
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(label_ref (match_operand 0 "" "")))]
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@ -1215,62 +1370,13 @@
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(set_attr "cc" "unchanged")])
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;;
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;; define insns for loops
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;; subtract, test and branch are tied together and the test can be omitted
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;;
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;; while (--foo > 0)
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(define_insn ""
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[(set (pc)
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(if_then_else
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(gt (plus:SI (match_operand:SI 0 "int_reg_operand" "+r")
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(const_int -1))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:SI (match_dup 0)
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(const_int -1)))]
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""
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"subq $1,%0\;brgt %l1")
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;; while (--foo >= 0)
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;;
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;; this does not work and I don't know why
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;; gcc 2.3.3 says that is doesn't match its contraint ?!?
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;; the problem seem to be the "+r" constraint. "r" works, but is this okay??
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;; Combiners for 'decrement test and branch' do not work for clipper.
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;; These patters are jump_insns that do not allow output reloads and clipper
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;; can only decrement and test registers.
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;;
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;;(define_insn ""
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;; [(set (pc)
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;; (if_then_else
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;; (ge (plus:SI (match_operand:SI 0 "int_reg_operand" "+r")
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;; (const_int -1))
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;; (const_int 0))
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;; (label_ref (match_operand 1 "" ""))
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;; (pc)))
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;; (set (match_dup 0)
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;; (plus:SI (match_dup 0)
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;; (const_int -1)))]
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;; ""
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;; "subq $1,%0\;brge %l1")
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;; `while (foo--)' -> `while (--foo != -1)'.
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(define_insn ""
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[(set (pc)
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(if_then_else
|
||||
(ne (match_operand:SI 0 "int_reg_operand" "+r")
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))]
|
||||
""
|
||||
"subq $1,%0\;brgeu %l1")
|
||||
|
||||
|
||||
;;- Local variables:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user