*** empty log message ***
From-SVN: r788
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Jim Wilson
parent
56a2f04910
commit
3501632240
@ -2250,6 +2250,107 @@ output_arc_profiler (arcno, insert_after)
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emit_insn_after (gen_rtx (SET, VOIDmode, mem_ref, profiler_reg),
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insert_after);
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}
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/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
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This makes them candidates for using ldd and std insns.
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Note reg1 and reg2 *must* be hard registers. To be sure we will
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abort if we are passed pseudo registers. */
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int
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registers_ok_for_ldd (reg1, reg2)
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rtx reg1, reg2;
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{
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/* We might have been passed a SUBREG. */
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if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
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return 0;
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/* Should never happen. */
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if (REGNO (reg1) > FIRST_PSEUDO_REGISTER
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|| REGNO (reg2) > FIRST_PSEUDO_REGISTER)
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abort ();
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if (REGNO (reg1) % 2 != 0)
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return 0;
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return (REGNO (reg1) == REGNO (reg2) - 1);
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}
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/* Return 1 if addr1 and addr2 are suitable for use in an ldd or
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std insn.
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This can only happen when addr1 and addr2 are consecutive memory
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locations (addr1 + 4 == addr2). addr1 must also be aligned on a
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64 bit boundary (addr1 % 8 == 0).
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We know %sp and %fp are kept aligned on a 64 bit boundary. Other
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registers are assumed to *never* be properly aligned and are
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rejected.
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Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
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need only check that the offset for addr1 % 8 == 0. */
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int
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memory_ok_for_ldd (addr1, addr2)
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rtx addr1, addr2;
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{
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int reg1, offset1;
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/* Extract a register number and offset (if used) from the first addr. */
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if (GET_CODE (addr1) == PLUS)
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{
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/* If not a REG, return zero. */
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if (GET_CODE (XEXP (addr1, 0)) != REG)
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return 0;
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else
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{
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reg1 = REGNO (XEXP (addr1, 0));
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/* The offset must be constant! */
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if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
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return 0;
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offset1 = INTVAL (XEXP (addr1, 1));
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}
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}
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else if (GET_CODE (addr1) != REG)
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return 0;
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else
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{
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reg1 = REGNO (addr1);
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/* This was a simple (mem (reg)) expression. Offset is 0. */
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offset1 = 0;
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}
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/* Make sure the second address is a (mem (plus (reg) (const_int). */
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if (GET_CODE (addr2) != PLUS)
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return 0;
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if (GET_CODE (XEXP (addr2, 0)) != REG
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|| GET_CODE (XEXP (addr2, 1)) != CONST_INT)
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return 0;
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/* Only %fp and %sp are allowed. Additionally both addresses must
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use the same register. */
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if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
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return 0;
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if (reg1 != REGNO (XEXP (addr2, 0)))
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return 0;
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/* The first offset must be evenly divisable by 8 to ensure the
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address is 64 bit aligned. */
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if (offset1 % 8 != 0)
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return 0;
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/* The offset for the second addr must be 4 more than the first addr. */
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if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
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return 0;
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/* All the tests passed. addr1 and addr2 are valid for ldd and std
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instructions. */
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return 1;
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}
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/* Print operand X (an rtx) in assembler syntax to file FILE.
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CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
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@ -2584,6 +2584,90 @@
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;; Peepholes go at the end.
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;; Optimize consecutive loads or stores into ldd and std when possible.
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;; The conditions in which we do this are very restricted and are
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;; explained in the code for {registers,memory}_ok_for_ldd functions.
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(define_peephole
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[(set (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "memory_operand" ""))
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(set (match_operand:SI 2 "register_operand" "r")
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(match_operand:SI 3 "memory_operand" ""))]
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"registers_ok_for_ldd (operands[0], operands[2])
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&& ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
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&& memory_ok_for_ldd (XEXP (operands[1], 0), XEXP (operands[3], 0))"
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"ldd %1,%0")
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(define_peephole
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[(set (match_operand:SI 0 "memory_operand" "")
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(match_operand:SI 1 "register_operand" "r"))
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(set (match_operand:SI 2 "memory_operand" "")
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(match_operand:SI 3 "register_operand" "r"))]
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"registers_ok_for_ldd (operands[1], operands[3])
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&& ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
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&& memory_ok_for_ldd (XEXP (operands[0], 0), XEXP (operands[2], 0))"
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"std %1,%0")
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(define_peephole
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[(set (match_operand:SF 0 "register_operand" "fr")
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(match_operand:SF 1 "memory_operand" ""))
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(set (match_operand:SF 2 "register_operand" "fr")
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(match_operand:SF 3 "memory_operand" ""))]
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"registers_ok_for_ldd (operands[0], operands[2])
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&& ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
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&& memory_ok_for_ldd (XEXP (operands[1], 0), XEXP (operands[3], 0))"
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"ldd %1,%0")
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(define_peephole
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[(set (match_operand:SF 0 "memory_operand" "")
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(match_operand:SF 1 "register_operand" "fr"))
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(set (match_operand:SF 2 "memory_operand" "")
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(match_operand:SF 3 "register_operand" "fr"))]
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"registers_ok_for_ldd (operands[1], operands[3])
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&& ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
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&& memory_ok_for_ldd (XEXP (operands[0], 0), XEXP (operands[2], 0))"
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"std %1,%0")
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(define_peephole
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[(set (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "memory_operand" ""))
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(set (match_operand:SI 2 "register_operand" "r")
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(match_operand:SI 3 "memory_operand" ""))]
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"registers_ok_for_ldd (operands[2], operands[0])
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&& ! MEM_VOLATILE_P (operands[3]) && ! MEM_VOLATILE_P (operands[1])
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&& memory_ok_for_ldd (XEXP (operands[3], 0), XEXP (operands[1], 0))"
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"ldd %3,%2")
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(define_peephole
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[(set (match_operand:SI 0 "memory_operand" "")
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(match_operand:SI 1 "register_operand" "r"))
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(set (match_operand:SI 2 "memory_operand" "")
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(match_operand:SI 3 "register_operand" "r"))]
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"registers_ok_for_ldd (operands[3], operands[1])
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&& ! MEM_VOLATILE_P (operands[2]) && ! MEM_VOLATILE_P (operands[0])
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&& memory_ok_for_ldd (XEXP (operands[2], 0), XEXP (operands[0], 0))"
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"std %3,%2")
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(define_peephole
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[(set (match_operand:SF 0 "register_operand" "fr")
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(match_operand:SF 1 "memory_operand" ""))
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(set (match_operand:SF 2 "register_operand" "fr")
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(match_operand:SF 3 "memory_operand" ""))]
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"registers_ok_for_ldd (operands[2], operands[0])
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&& ! MEM_VOLATILE_P (operands[3]) && ! MEM_VOLATILE_P (operands[1])
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&& memory_ok_for_ldd (XEXP (operands[3], 0), XEXP (operands[1], 0))"
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"ldd %3,%2")
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(define_peephole
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[(set (match_operand:SF 0 "memory_operand" "")
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(match_operand:SF 1 "register_operand" "fr"))
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(set (match_operand:SF 2 "memory_operand" "")
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(match_operand:SF 3 "register_operand" "fr"))]
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"registers_ok_for_ldd (operands[3], operands[1])
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&& ! MEM_VOLATILE_P (operands[2]) && ! MEM_VOLATILE_P (operands[0])
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&& memory_ok_for_ldd (XEXP (operands[2], 0), XEXP (operands[0], 0))"
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"std %3,%2")
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;; Optimize the case of following a reg-reg move with a test
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;; of reg just moved.
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