c4x.h (TARGET_DEFAULT): Add PARALEL_MPY_FLAG.
* config/c4x/c4x.h (TARGET_DEFAULT): Add PARALEL_MPY_FLAG. (TARGET_SMALL_REG_CLASS): Set to 0 so that SMALL_REGISTER_CLASSES is no longer enabled if PARALLEL_MPY_FLAG set. (HARD_REGNO_CALL_CLOBBERED): Add parentheses to remove ambiguity. (REG_CLASS_CONTENTS): Add braces around initializers. (HAVE_MULTIPLE_PACK): Define. (ASM_OUTPUT_BYTE_FLOAT): Use %lf format specifier with REAL_VALUE_TO_DECIMAL. (ASM_OUTPUT_SHORT_FLOAT): Use %lf format specifier with REAL_VALUE_TO_DECIMAL. (ar0_reg_operand): Add prototype. (ar0_mem_operand): Likewise. (ar1_reg_operand): Likewise. (ar1_mem_operand): Likewise. (ar2_reg_operand): Likewise. (ar2_mem_operand): Likewise. (ar3_reg_operand): Likewise. (ar3_mem_operand): Likewise. (ar4_reg_operand): Likewise. (ar4_mem_operand): Likewise. (ar5_reg_operand): Likewise. (ar5_mem_operand): Likewise. (ar6_reg_operand): Likewise. (ar6_mem_operand): Likewise. (ar7_reg_operand): Likewise. (ar7_mem_operand): Likewise. (ir0_reg_operand): Likewise. (ir0_mem_operand): Likewise. (ir1_reg_operand): Likewise. (ir1_mem_operand): Likewise. (group1_reg_operand): Likewise. (group1_mem_operand): Likewise. (ir1_reg_operand): Likewise. (arx_reg_operand): Likewise. (not_rc_reg): Likewise. (not_modify_reg): Likewise. (c4x_group1_reg_operand): Remove prototype. (c4x_group1_mem_operand): Likewise. (c4x_arx_reg_operand): Likewise. From-SVN: r23876
This commit is contained in:
Michael Hayes
Michael Hayes
parent
3c9a0d0fed
commit
2e3e9ead11
@ -1,3 +1,45 @@
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Thu Nov 26 14:56:32 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.h (TARGET_DEFAULT): Add PARALEL_MPY_FLAG.
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(TARGET_SMALL_REG_CLASS): Set to 0 so that SMALL_REGISTER_CLASSES
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is no longer enabled if PARALLEL_MPY_FLAG set.
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(HARD_REGNO_CALL_CLOBBERED): Add parentheses to remove ambiguity.
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(REG_CLASS_CONTENTS): Add braces around initializers.
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(HAVE_MULTIPLE_PACK): Define.
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(ASM_OUTPUT_BYTE_FLOAT): Use %lf format specifier with
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REAL_VALUE_TO_DECIMAL.
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(ASM_OUTPUT_SHORT_FLOAT): Use %lf format specifier with
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REAL_VALUE_TO_DECIMAL.
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(ar0_reg_operand): Add prototype.
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(ar0_mem_operand): Likewise.
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(ar1_reg_operand): Likewise.
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(ar1_mem_operand): Likewise.
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(ar2_reg_operand): Likewise.
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(ar2_mem_operand): Likewise.
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(ar3_reg_operand): Likewise.
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(ar3_mem_operand): Likewise.
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(ar4_reg_operand): Likewise.
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(ar4_mem_operand): Likewise.
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(ar5_reg_operand): Likewise.
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(ar5_mem_operand): Likewise.
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(ar6_reg_operand): Likewise.
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(ar6_mem_operand): Likewise.
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(ar7_reg_operand): Likewise.
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(ar7_mem_operand): Likewise.
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(ir0_reg_operand): Likewise.
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(ir0_mem_operand): Likewise.
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(ir1_reg_operand): Likewise.
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(ir1_mem_operand): Likewise.
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(group1_reg_operand): Likewise.
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(group1_mem_operand): Likewise.
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(ir1_reg_operand): Likewise.
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(arx_reg_operand): Likewise.
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(not_rc_reg): Likewise.
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(not_modify_reg): Likewise.
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(c4x_group1_reg_operand): Remove prototype.
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(c4x_group1_mem_operand): Likewise.
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(c4x_arx_reg_operand): Likewise.
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Wed Nov 25 19:02:55 1998 (Stephen L Moshier) <moshier@world.std.com>
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* emit-rtl.c (gen_lowpart_common): Remove earlier change.
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@ -211,11 +211,9 @@
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/* Default target switches */
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/* Play safe, not the fastest code. Note that setting PARALLEL_MPY
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flag will set SMALL_REGISTER_CLASSES which can be a price to pay,
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especially when MPY||ADD instructions are only generated very
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infrequenctly. */
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#define TARGET_DEFAULT ALIASES_FLAG | RPTB_FLAG | PARALLEL_PACK_FLAG
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/* Play safe, not the fastest code. */
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#define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_PACK_FLAG \
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| PARALLEL_MPY_FLAG | TARGET_RPTB_FLAG
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/* Caveats:
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Max iteration count for RPTB/RPTS is 2^31 + 1.
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@ -227,7 +225,7 @@ extern int target_flags;
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#define TARGET_INLINE 1 /* Inline MPYI */
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#define TARGET_PARALLEL 1 /* Enable parallel insns in MD */
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#define TARGET_SMALL_REG_CLASS 1
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#define TARGET_SMALL_REG_CLASS 0
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#define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
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#define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
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@ -534,6 +532,11 @@ extern void c4x_optimization_options ();
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c4x_regclass_map[i] = NO_REGS; \
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} \
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} \
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if (TARGET_PRESERVE_FLOAT) \
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{ \
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c4x_caller_save_map[R6_REGNO] = HFmode; \
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c4x_caller_save_map[R7_REGNO] = HFmode; \
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} \
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}
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/* Order of Allocation of Registers */
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@ -579,11 +582,10 @@ extern void c4x_optimization_options ();
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across a call in mode MODE. This does not have to include the call used
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registers. */
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#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
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(((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) \
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&& (MODE) != QFmode \
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|| ((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO) \
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&& ((MODE) != QImode || (MODE) != HImode || (MODE) != Pmode)))
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#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
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((((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) && ! ((MODE) == QFmode)) \
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|| (((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO)) \
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&& ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
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/* Specify the modes required to caller save a given hard regno. */
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@ -668,26 +670,27 @@ enum reg_class
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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of length N_REG_CLASSES. */
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of length N_REG_CLASSES. RC is not included in GENERAL_REGS
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since the register allocator will often choose a general register
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in preference to RC for the decrement_and_branch_on_count pattern. */
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#define REG_CLASS_CONTENTS \
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{ \
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0x00000000, /* No registers */ \
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0x00000003, /* 't' R0-R1 */ \
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0x0000000c, /* 'u' R2-R3 */ \
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0x000000ff, /* 'q' R0-R7 */ \
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0xf00000ff, /* 'f' R0-R11 */ \
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0x0000ff00, /* 'a' AR0-AR7 */ \
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0x00060000, /* 'x' IR0-IR1 */ \
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0x00080000, /* 'k' BK */ \
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0x00100000, /* 'b' SP */ \
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0x08000000, /* 'v' RC */ \
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0x0e1eff00, /* 'c' AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */ \
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0xfe1effff, /* 'r' R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */\
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0x00010000, /* 'z' DP */ \
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0x00200000, /* 'y' ST */ \
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0xffffffff, /* All registers */ \
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{0x00000000}, /* No registers */ \
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{0x00000003}, /* 't' R0-R1 */ \
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{0x0000000c}, /* 'u' R2-R3 */ \
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{0x000000ff}, /* 'q' R0-R7 */ \
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{0xf00000ff}, /* 'f' R0-R11 */ \
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{0x0000ff00}, /* 'a' AR0-AR7 */ \
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{0x00060000}, /* 'x' IR0-IR1 */ \
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{0x00080000}, /* 'k' BK */ \
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{0x00100000}, /* 'b' SP */ \
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{0x08000000}, /* 'v' RC */ \
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{0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */ \
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{0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */\
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{0x00010000}, /* 'z' DP */ \
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{0x00200000}, /* 'y' ST */ \
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{0xffffffff}, /* All registers */ \
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}
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/* The same information, inverted:
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@ -697,22 +700,18 @@ enum reg_class
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#define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
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/* When SMALL_REGISTER_CLASSES is defined, the compiler allows
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registers explicitly used in the rtl to be used as spill registers but
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prevents the compiler from extending the lifetime of these registers.
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Problems can occur if reload has to spill a register used explicitly
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in the RTL if it has a long lifetime. This is only likely to be a problem
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with a function having many variables and thus lots of spilling.
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/* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
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explicitly used in the rtl is kept as short as possible.
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We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
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is defined since the MPY|ADD insns require the classes R0R1_REGS and
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R2R3_REGS which are used by the function return registers (R0,R1) and
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the register arguments (R2,R3), respectively. I'm reluctant to define
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this macro since it stomps on many potential optimisations. Ideally
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it should have a register class argument so that not all the register
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classes gets penalised for the sake of a naughty few... For long
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double arithmetic we need two additional registers that we can use as
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spill registers. */
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We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
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is defined since the MPY|ADD insns require the classes R0R1_REGS and
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R2R3_REGS which are used by the function return registers (R0,R1) and
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the register arguments (R2,R3), respectively. I'm reluctant to define
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this macro since it stomps on many potential optimisations. Ideally
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it should have a register class argument so that not all the register
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classes gets penalised for the sake of a naughty few... For long
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double arithmetic we need two additional registers that we can use as
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spill registers. */
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#define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
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@ -720,7 +719,7 @@ spill registers. */
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#define INDEX_REG_CLASS INDEX_REGS
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/*
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Constraints for the C4x
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Register constraints for the C4x
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a - address reg (ar0-ar7)
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b - stack reg (sp)
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@ -737,6 +736,8 @@ spill registers. */
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y - status register (st)
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z - dp reg (dp)
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Memory/constant constraints for the C4x
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G - short float 16-bit
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I - signed 16-bit constant (sign extended)
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J - signed 8-bit constant (sign extended) (C4x only)
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@ -1528,6 +1529,8 @@ extern struct rtx_def *c4x_gen_compare_reg ();
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#define HAVE_PRE_MODIFY_DISP 1
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#define HAVE_POST_MODIFY_DISP 1
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#define HAVE_MULTIPLE_PACK 2
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/* What about LABEL_REF? */
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#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
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@ -1976,7 +1979,7 @@ dtors_section () \
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{ long l; \
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char str[30]; \
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REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
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REAL_VALUE_TO_DECIMAL (VALUE, "%20f", str); \
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REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
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if (sizeof (int) == sizeof (long)) \
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fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
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else \
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@ -1995,7 +1998,7 @@ dtors_section () \
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{ long l[2]; \
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char str[30]; \
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REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
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REAL_VALUE_TO_DECIMAL (VALUE, "%20f", str); \
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REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
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l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
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if (sizeof (int) == sizeof (long)) \
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fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
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@ -2580,10 +2583,60 @@ extern int rc_reg_operand ();
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extern int st_reg_operand ();
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extern int ar0_reg_operand ();
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extern int ar0_mem_operand ();
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extern int ar1_reg_operand ();
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extern int ar1_mem_operand ();
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extern int ar2_reg_operand ();
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extern int ar2_mem_operand ();
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extern int ar3_reg_operand ();
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extern int ar3_mem_operand ();
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extern int ar4_reg_operand ();
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extern int ar4_mem_operand ();
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extern int ar5_reg_operand ();
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extern int ar5_mem_operand ();
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extern int ar6_reg_operand ();
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extern int ar6_mem_operand ();
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extern int ar7_reg_operand ();
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extern int ar7_mem_operand ();
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extern int ir0_reg_operand ();
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extern int ir0_mem_operand ();
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extern int ir1_reg_operand ();
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extern int ir1_mem_operand ();
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extern int group1_reg_operand ();
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extern int group1_mem_operand ();
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extern int arx_reg_operand ();
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extern int call_operand ();
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extern int par_ind_operand ();
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extern int not_rc_reg ();
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extern int not_modify_reg ();
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extern int c4x_H_constant ();
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extern int c4x_I_constant ();
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@ -2606,12 +2659,6 @@ extern void c4x_emit_libcall3 ();
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extern void c4x_emit_libcall_mulhi ();
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extern int c4x_group1_reg_operand ();
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extern int c4x_group1_mem_operand ();
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extern int c4x_arx_reg_operand ();
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extern int legitimize_operands ();
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extern int valid_operands ();
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