aarch64: Fix mismatched SVE predicate modes [PR94606]
For this testcase we ended up generating the invalid rtl:
(insn 10 9 11 2 (set (reg:VNx16BI 105)
(and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
(reg:VNx16BI 104))
(reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
(nil))
Fixed by taking the VNx16BI lowpart. It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.
2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/94606
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
the VNx16BI lowpart of the recursively-generated constant.
gcc/testsuite/
PR target/94606
* gcc.dg/vect/pr94606.c: New test.
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2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
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PR target/94606
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* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
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the VNx16BI lowpart of the recursively-generated constant.
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2020-04-16 Martin Liska <mliska@suse.cz>
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Jakub Jelinek <jakub@redhat.com>
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@ -4742,6 +4742,7 @@ aarch64_expand_sve_const_pred_eor (rtx target, rtx_vector_builder &builder,
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/* EOR the result with an ELT_SIZE PTRUE. */
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rtx mask = aarch64_ptrue_all (elt_size);
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mask = force_reg (VNx16BImode, mask);
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inv = gen_lowpart (VNx16BImode, inv);
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target = aarch64_target_reg (target, VNx16BImode);
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emit_insn (gen_aarch64_pred_z (XOR, VNx16BImode, target, mask, inv, mask));
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return target;
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@ -1,3 +1,8 @@
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2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
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PR target/94606
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* gcc.dg/vect/pr94606.c: New test.
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2020-04-16 Martin Liska <mliska@suse.cz>
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Jakub Jelinek <jakub@redhat.com>
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13
gcc/testsuite/gcc.dg/vect/pr94606.c
Normal file
13
gcc/testsuite/gcc.dg/vect/pr94606.c
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/* { dg-do compile } */
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/* { dg-additional-options "-march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64*-*-* } } */
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const short mask[] = { 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 1, 1, 1, 1 };
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int
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foo (short *restrict x, short *restrict y)
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{
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for (int i = 0; i < 16; ++i)
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if (mask[i])
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x[i] += y[i];
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}
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