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sparc.md (movsf_const_intreg): Add constraints for regclass' sake.

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* config/sparc/sparc.md (movsf_const_intreg): Add constraints for
	regclass' sake.
	(movdf_const_intreg_sp32): Likewise. Prefer the memory load
	alternative because setting up 64bit constant is usually costly,
	especially when reload is in progress or completed.
	(movdf_const_intreg_sp64): Likewise.
	(movdf_const_intreg split): Fix building up constants when
	HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit.

From-SVN: r30750
This commit is contained in:
Jakub Jelinek 1999-12-02 01:38:56 +01:00 committed by David S. Miller
parent e8758a3a01
commit 119a467780
2 changed files with 18 additions and 7 deletions
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11
gcc/ChangeLog
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@ -1,3 +1,14 @@
1999-12-01 Jakub Jelinek <jakub@redhat.com>
* config/sparc/sparc.md (movsf_const_intreg): Add constraints for
regclass' sake.
(movdf_const_intreg_sp32): Likewise. Prefer the memory load
alternative because setting up 64bit constant is usually costly,
especially when reload is in progress or completed.
(movdf_const_intreg_sp64): Likewise.
(movdf_const_intreg split): Fix building up constants when
HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit.
Wed Dec 1 16:51:22 1999 Jeffrey A Law (law@cygnus.com) Wed Dec 1 16:51:22 1999 Jeffrey A Law (law@cygnus.com)
* combine.c (if_then_else_cond): Use const_true_rtx instead of * combine.c (if_then_else_cond): Use const_true_rtx instead of

14
gcc/config/sparc/sparc.md
View File

@ -2765,7 +2765,7 @@
(define_insn "*movsf_const_intreg" (define_insn "*movsf_const_intreg"
[(set (match_operand:SF 0 "register_operand" "=f,r") [(set (match_operand:SF 0 "register_operand" "=f,r")
(match_operand:SF 1 "const_double_operand" "m,F"))] (match_operand:SF 1 "const_double_operand" "m#F,F"))]
"TARGET_FPU" "TARGET_FPU"
"* "*
{ {
@ -2932,8 +2932,8 @@
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*movdf_const_intreg_sp32" (define_insn "*movdf_const_intreg_sp32"
[(set (match_operand:DF 0 "register_operand" "=e,e,r") [(set (match_operand:DF 0 "register_operand" "=e,e,?r")
(match_operand:DF 1 "const_double_operand" "T,o,F"))] (match_operand:DF 1 "const_double_operand" "T#F,o#F,F"))]
"TARGET_FPU && ! TARGET_ARCH64" "TARGET_FPU && ! TARGET_ARCH64"
"@ "@
ldd\\t%1, %0 ldd\\t%1, %0
@ -2945,8 +2945,8 @@
;; Now that we redo life analysis with a clean slate after ;; Now that we redo life analysis with a clean slate after
;; instruction splitting for sched2 this can work. ;; instruction splitting for sched2 this can work.
(define_insn "*movdf_const_intreg_sp64" (define_insn "*movdf_const_intreg_sp64"
[(set (match_operand:DF 0 "register_operand" "=e,r") [(set (match_operand:DF 0 "register_operand" "=e,?r")
(match_operand:DF 1 "const_double_operand" "m,F"))] (match_operand:DF 1 "const_double_operand" "m#F,F"))]
"TARGET_FPU && TARGET_ARCH64" "TARGET_FPU && TARGET_ARCH64"
"@ "@
ldd\\t%1, %0 ldd\\t%1, %0
@ -2978,8 +2978,8 @@
#if HOST_BITS_PER_WIDE_INT == 64 #if HOST_BITS_PER_WIDE_INT == 64
HOST_WIDE_INT val; HOST_WIDE_INT val;
val = ((HOST_WIDE_INT)l[1] | val = ((HOST_WIDE_INT)(unsigned long)l[1] |
((HOST_WIDE_INT)l[0] << 32)); ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
emit_insn (gen_movdi (operands[0], GEN_INT (val))); emit_insn (gen_movdi (operands[0], GEN_INT (val)));
#else #else
emit_insn (gen_movdi (operands[0], emit_insn (gen_movdi (operands[0],