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rs6000: Fix some unexpected empty split conditions

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This patch is to fix empty split-conditions of some
define_insn_and_split definitions where their conditions for
define_insn part aren't empty.  As Segher and Mike pointed
out, they can sometimes lead to unexpected consequences.

Bootstrapped/regtested on powerpc64le-linux-gnu P9 and
powerpc64-linux-gnu P8.

gcc/ChangeLog:

	* config/rs6000/rs6000.md (*rotldi3_insert_sf,
	*mov<SFDF:mode><SFDF2:mode>cc_p9, floatsi<mode>2_lfiwax,
	floatsi<mode>2_lfiwax_mem, floatunssi<mode>2_lfiwzx,
	floatunssi<mode>2_lfiwzx_mem, *floatsidf2_internal,
	*floatunssidf2_internal, fix_trunc<mode>si2_stfiwx,
	fix_trunc<mode>si2_internal, fixuns_trunc<mode>si2_stfiwx,
	*round32<mode>2_fprs, *roundu32<mode>2_fprs,
	*fix_trunc<mode>si2_internal): Fix empty split condition.
	* config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
	vsx_reduc_<VEC_reduc_name>_v2df, vsx_reduc_<VEC_reduc_name>_v4sf,
	*vsx_reduc_<VEC_reduc_name>_v2df_scalar,
	*vsx_reduc_<VEC_reduc_name>_v4sf_scalar): Likewise.
This commit is contained in:
Kewen Lin 2021-03-18 01:22:59 -05:00
parent d0a5e8e1a8
commit 0ec7641ee1
2 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
gcc/config/rs6000/rs6000.md
View File

@ -4286,7 +4286,7 @@
(clobber (match_scratch:V4SF 4))]
"TARGET_POWERPC64 && INTVAL (operands[2]) == <bits>"
"#"
""
"&& 1"
[(parallel [(set (match_dup 5)
(zero_extend:DI (unspec:QHSI [(match_dup 3)] UNSPEC_SI_FROM_SF)))
(clobber (match_dup 4))])
@ -5332,7 +5332,7 @@
(clobber (match_scratch:V2DI 6 "=0,&wa"))]
"TARGET_P9_MINMAX"
"#"
""
"&& 1"
[(set (match_dup 6)
(if_then_else:V2DI (match_dup 1)
(match_dup 7)
@ -5441,7 +5441,7 @@
"TARGET_HARD_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -5481,7 +5481,7 @@
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
"&& 1"
[(pc)]
{
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
@ -5516,7 +5516,7 @@
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -5556,7 +5556,7 @@
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
"&& 1"
[(pc)]
{
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
@ -5621,7 +5621,7 @@
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"!TARGET_FCFID && TARGET_HARD_FLOAT"
"#"
""
"&& 1"
[(pc)]
{
rtx lowword, highword;
@ -5711,7 +5711,7 @@
"!TARGET_FCFIDU && TARGET_HARD_FLOAT
&& !(TARGET_FCFID && TARGET_POWERPC64)"
"#"
""
"&& 1"
[(pc)]
{
rtx lowword, highword;
@ -5867,7 +5867,7 @@
"TARGET_HARD_FLOAT && TARGET_STFIWX && can_create_pseudo_p ()
&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -5909,7 +5909,7 @@
"TARGET_HARD_FLOAT
&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
"#"
""
"&& 1"
[(pc)]
{
rtx lowword;
@ -6015,7 +6015,7 @@
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_P8_VECTOR"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -6235,7 +6235,7 @@
&& <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
&& !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -6268,7 +6268,7 @@
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
&& can_create_pseudo_p ()"
"#"
""
"&& 1"
[(pc)]
{
rtx dest = operands[0];
@ -8251,7 +8251,7 @@
(clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
""
"&& 1"
[(pc)]
{
rtx lowword;

10
gcc/config/rs6000/vsx.md
View File

@ -972,7 +972,7 @@
"@
#
xxlor %x0,%x1"
""
"&& 1"
[(set (match_dup 0) (match_dup 1))]
{
if (reload_completed && REGNO (operands[0]) == REGNO (operands[1]))
@ -4656,7 +4656,7 @@
(clobber (match_scratch:V2DF 2 "=0,&wa"))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"#"
""
"&& 1"
[(const_int 0)]
{
rtx tmp = (GET_CODE (operands[2]) == SCRATCH)
@ -4678,7 +4678,7 @@
(clobber (match_scratch:V4SF 3 "=&wa"))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""
"&& 1"
[(const_int 0)]
{
rtx op0 = operands[0];
@ -4726,7 +4726,7 @@
(clobber (match_scratch:DF 2 "=0,&wa"))]
"BYTES_BIG_ENDIAN && VECTOR_UNIT_VSX_P (V2DFmode)"
"#"
""
"&& 1"
[(const_int 0)]
{
rtx hi = gen_highpart (DFmode, operands[1]);
@ -4753,7 +4753,7 @@
(clobber (match_scratch:V4SF 4 "=0"))]
"BYTES_BIG_ENDIAN && VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""
"&& 1"
[(const_int 0)]
{
rtx op0 = operands[0];