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Fix coldfire/btst problems.

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* m68k.md (btst patterns): Add 5200 support.

From-SVN: r16217
This commit is contained in:
Jim Wilson 1997-10-28 19:56:50 +00:00 committed by Jim Wilson
parent 750e83485a
commit 0841747819
2 changed files with 45 additions and 3 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
Tue Oct 28 11:53:14 1997 Jim Wilson <wilson@cygnus.com>
* m68k.md (btst patterns): Add 5200 support.
Tue Oct 28 11:58:40 1997 Toon Moene <toon@moene.indiv.nluug.nl>
* fold-const.c (fold): For ((a * C1) / C3) or (((a * C1) + C2) / C3)

44
gcc/config/m68k/m68k.md
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@ -749,12 +749,27 @@
;; Recognizers for btst instructions.
;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
;; specified as a constant, so we must disable all patterns that may extract
;; from a MEM at a constant bit position if we can't use this as a constraint.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
""
"!TARGET_5200"
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
;; This is the same as the above pattern except for the constraints. The 'i'
;; has been deleted.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "d"))))]
"TARGET_5200"
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
@ -795,7 +810,7 @@
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
"(unsigned) INTVAL (operands[1]) < 8"
"(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
"*
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
@ -806,7 +821,30 @@
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
""
"!TARGET_5200"
"*
{
if (GET_CODE (operands[0]) == MEM)
{
operands[0] = adj_offsettable_operand (operands[0],
INTVAL (operands[1]) / 8);
operands[1] = gen_rtx (CONST_INT, VOIDmode,
7 - INTVAL (operands[1]) % 8);
return output_btst (operands, operands[1], operands[0], insn, 7);
}
operands[1] = gen_rtx (CONST_INT, VOIDmode,
31 - INTVAL (operands[1]));
return output_btst (operands, operands[1], operands[0], insn, 31);
}")
;; This is the same as the above pattern except for the constraints.
;; The 'o' has been replaced with 'Q'.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
"TARGET_5200"
"*
{
if (GET_CODE (operands[0]) == MEM)