({add,sub}di{_mem,3}): Patterns merged.
From-SVN: r9926
This commit is contained in:
Richard Kenner
parent
76ffb3a0be
commit
055c15842a
@ -2050,57 +2050,57 @@
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return \"add%.l %1,%0\";
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} ")
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(define_insn "adddi_mem"
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[(set (match_operand:DI 0 "general_operand" "=o,<,>")
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(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0")
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(match_operand:DI 2 "general_operand" "d,d,d")))
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(clobber (match_scratch:SI 3 "=d,d,d"))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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if (which_alternative == 2)
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{
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operands[1] = gen_rtx (MEM, SImode,
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gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
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gen_rtx (CONST_INT, VOIDmode, -8)));
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return \"move%.l %0,%3\;add%.l %4,%0\;addx%.l %2,%3\;move%.l %3,%1\";
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}
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if (which_alternative == 1)
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{
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operands[1] = XEXP(operands[0], 0);
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return \"add%.l %4,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
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}
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"add%.l %4,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
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} ")
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
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[(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
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(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
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(match_operand:DI 2 "general_operand" "*ao,>,d,<")))]
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(match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
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(clobber (match_scratch:SI 3 "=X,X,d,d"))]
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""
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"*
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{
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if (which_alternative == 3)
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return \"add%.l %2,%0\;addx%.l %2,%0\";
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (which_alternative == 1)
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if (DATA_REG_P (operands[0]))
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{
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CC_STATUS_INIT;
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return \"add%.l %2,%0\;add%.l %2,%1\;negx%.l %0\;neg%.l %0\";
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if (DATA_REG_P (operands[2]))
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return \"add%.l %R2,%R0\;addx%.l %2,%0\";
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else if (GET_CODE (operands[2]) == MEM
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&& GET_CODE (XEXP (operands[2], 0)) == POST_INC)
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{
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return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
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}
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else
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{
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/* TODO : this should work also for CONST operands[2] */
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if (GET_CODE (operands[2]) == REG)
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[1] = adj_offsettable_operand (operands[2], 4);
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return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
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}
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}
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else if (GET_CODE (operands[0]) == MEM)
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{
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if (GET_CODE (operands[2]) == MEM
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&& GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
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return \"add%.l %2,%0\;addx%.l %2,%0\";
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CC_STATUS_INIT;
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if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
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{
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operands[1] = gen_rtx (MEM, SImode,
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gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
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gen_rtx (CONST_INT, VOIDmode, -8)));
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return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
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}
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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{
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operands[1] = XEXP(operands[0], 0);
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return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
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}
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else
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{
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
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}
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}
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if (GET_CODE (operands[2]) == REG)
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[3] = adj_offsettable_operand (operands[2], 4);
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if (which_alternative == 2)
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return \"add%.l %3,%1\;addx%.l %2,%0\";
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CC_STATUS_INIT;
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/* negx + neg simulates (non-existent) addx #0 */
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/* TODO : this should work also for CONST operands[2] */
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return \"add%.l %3,%1\;negx%.l %0\;neg%.l %0\;add%.l %2,%0\";
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} ")
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(define_insn "addsi_lshrsi_31"
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@ -2639,57 +2639,57 @@
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return \"sub%.l %1,%0\";
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} ")
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(define_insn "subdi_mem"
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[(set (match_operand:DI 0 "general_operand" "=o,<,>")
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(minus:DI (match_operand:DI 1 "general_operand" "0,0,0")
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(match_operand:DI 2 "register_operand" "d,d,d")))
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(clobber (match_scratch:SI 3 "=d,d,d"))]
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""
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"*
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{
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CC_STATUS_INIT;
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operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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if (which_alternative == 2)
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{
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operands[1] = gen_rtx (MEM, SImode,
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gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
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gen_rtx (CONST_INT, VOIDmode, -8)));
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return \"move%.l %0,%3\;sub%.l %4,%0\;subx%.l %2,%3\;move%.l %3,%1\";
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}
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if (which_alternative == 1)
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{
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operands[1] = XEXP(operands[0], 0);
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return \"sub%.l %4,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
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}
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"sub%.l %4,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
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} ")
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
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(minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
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(match_operand:DI 2 "general_operand" "*ao,>,d,<")))]
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[(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
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(minus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
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(match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
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(clobber (match_scratch:SI 3 "=X,X,d,d"))]
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""
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"*
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{
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if (which_alternative == 3)
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return \"sub%.l %2,%0\;subx%.l %2,%0\";
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (which_alternative == 1)
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if (DATA_REG_P (operands[0]))
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{
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CC_STATUS_INIT;
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return \"neg%.l %0\;add%.l %2,%0\;sub%.l %2,%1\;negx%.l %0\";
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if (DATA_REG_P (operands[2]))
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return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
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else if (GET_CODE (operands[2]) == MEM
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&& GET_CODE (XEXP (operands[2], 0)) == POST_INC)
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{
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return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
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}
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else
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{
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/* TODO : this should work also for CONST operands[2] */
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if (GET_CODE (operands[2]) == REG)
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[1] = adj_offsettable_operand (operands[2], 4);
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return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
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}
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}
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else if (GET_CODE (operands[0]) == MEM)
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{
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if (GET_CODE (operands[2]) == MEM
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&& GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
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return \"sub%.l %2,%0\;subx%.l %2,%0\";
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CC_STATUS_INIT;
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if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
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{
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operands[1] = gen_rtx (MEM, SImode,
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gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
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gen_rtx (CONST_INT, VOIDmode, -8)));
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return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
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}
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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{
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operands[1] = XEXP(operands[0], 0);
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return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
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}
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else
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{
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
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}
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}
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if (GET_CODE (operands[2]) == REG)
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operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
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else
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operands[3] = adj_offsettable_operand (operands[2], 4);
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if (which_alternative == 2)
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return \"sub%.l %3,%1\;subx%.l %2,%0\";
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CC_STATUS_INIT;
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/* neg + negx simulates (non-existent) subx #0 */
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/* TODO : this should work also for CONST operands[2] */
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return \"neg%.l %0\;sub%.l %3,%1\;negx%.l %0\;sub%.l %2,%0\";
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} ")
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(define_insn "subsi3"
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