(*zeroextract[qs]i_compare0_scratch): Use const_int_operand for operands 1 and 2.
(*zeroextract[qs]i_compare0_scratch): Use const_int_operand for operands 1 and 2. (split patterns for aligned memory half-word operations): New patterns. (movhi): Handle memory accesses where the alignment is known in a more efficient manner. (*compareqi_eq0): Use CC_Zmode. From-SVN: r11305
This commit is contained in:
Richard Earnshaw
parent
5165176d89
commit
0502226c85
@ -1012,8 +1012,8 @@
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[(set (reg:CC_NOOV 24)
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(compare:CC_NOOV (zero_extract:SI
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(match_operand:SI 0 "s_register_operand" "r")
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(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "immediate_operand" "n"))
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(match_operand 1 "const_int_operand" "n")
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(match_operand 2 "const_int_operand" "n"))
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(const_int 0)))]
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"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32
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&& INTVAL (operands[1]) > 0
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@ -1037,8 +1037,8 @@
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[(set (reg:CC_NOOV 24)
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(compare:CC_NOOV (zero_extract:SI
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(match_operand:QI 0 "memory_operand" "m")
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(match_operand 1 "immediate_operand" "n")
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(match_operand 2 "immediate_operand" "n"))
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(match_operand 1 "const_int_operand" "n")
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(match_operand 2 "const_int_operand" "n"))
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(const_int 0)))
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(clobber (match_scratch:QI 3 "=r"))]
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"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 8
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@ -1875,6 +1875,36 @@
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"ldr%?h\\t%0, %1"
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[(set_attr "type" "load")])
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
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(clobber (match_operand:SI 2 "s_register_operand" ""))]
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"! arm_arch4"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (lshiftrt:SI (match_dup 2) (const_int 16)))]
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"
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{
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if ((operands[1] = gen_rotated_half_load (operands[1])) == NULL)
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FAIL;
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}")
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(match_operator:SI 3 "shiftable_operator"
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[(zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
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(match_operand:SI 4 "s_register_operand" "")]))
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(clobber (match_operand:SI 2 "s_register_operand" ""))]
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"! arm_arch4"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0)
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(match_op_dup 3
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[(lshiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
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"
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{
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if ((operands[1] = gen_rotated_half_load (operands[1])) == NULL)
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FAIL;
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}")
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(define_expand "zero_extendqisi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(zero_extend:SI
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@ -1906,8 +1936,8 @@
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"")
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(define_insn "*compareqi_eq0"
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[(set (reg:CC_NOOV 24)
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(compare:CC_NOOV (match_operand:QI 0 "s_register_operand" "r")
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[(set (reg:CC_Z 24)
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(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
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(const_int 0)))]
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""
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"tst\\t%0, #255"
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@ -1975,6 +2005,36 @@
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"ldr%?sh\\t%0, %1"
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[(set_attr "type" "load")])
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
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(clobber (match_operand:SI 2 "s_register_operand" ""))]
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"! arm_arch4"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (ashiftrt:SI (match_dup 2) (const_int 16)))]
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"
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{
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if ((operands[1] = gen_rotated_half_load (operands[1])) == NULL)
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FAIL;
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}")
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(match_operator:SI 3 "shiftable_operator"
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[(sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
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(match_operand:SI 4 "s_register_operand" "")]))
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(clobber (match_operand:SI 2 "s_register_operand" ""))]
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"! arm_arch4"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0)
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(match_op_dup 3
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[(ashiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
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"
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{
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if ((operands[1] = gen_rotated_half_load (operands[1])) == NULL)
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FAIL;
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}")
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(define_expand "extendqihi2"
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[(set (match_dup 2)
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(ashift:SI (match_operand:QI 1 "general_operand" "")
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@ -2366,22 +2426,97 @@
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}
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else if (! arm_arch4)
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{
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if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
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if (GET_CODE (operands[1]) == MEM)
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{
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rtx reg = gen_reg_rtx (SImode);
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emit_insn (gen_movhi_bytes (reg, operands[1]));
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operands[1] = gen_lowpart (HImode, reg);
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}
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else if (BYTES_BIG_ENDIAN && GET_CODE (operands[1]) == MEM)
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{
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emit_insn (gen_movhi_bigend (operands[0], operands[1]));
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DONE;
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if (TARGET_SHORT_BY_BYTES)
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{
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rtx base;
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rtx offset = const0_rtx;
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rtx reg = gen_reg_rtx (SImode);
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if ((GET_CODE (base = XEXP (operands[1], 0)) == REG
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|| (GET_CODE (base) == PLUS
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&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT
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&& GET_CODE (base = XEXP (base, 0)) == REG))
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&& REGNO_POINTER_ALIGN (REGNO (base)) >= 4)
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{
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HOST_WIDE_INT new_offset = INTVAL (offset) & ~2;
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emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode,
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plus_constant (base, new_offset))));
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if (((INTVAL (offset) & 2) != 0)
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^ (BYTES_BIG_ENDIAN ? 1 : 0))
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{
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rtx reg2 = gen_reg_rtx (SImode);
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emit_insn (gen_lshrsi3 (reg2, reg, GEN_INT (16)));
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reg = reg2;
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}
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}
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else
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emit_insn (gen_movhi_bytes (reg, operands[1]));
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operands[1] = gen_lowpart (HImode, reg);
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}
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else if (BYTES_BIG_ENDIAN)
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{
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rtx base;
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rtx offset = const0_rtx;
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if ((GET_CODE (base = XEXP (operands[1], 0)) == REG
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|| (GET_CODE (base) == PLUS
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&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT
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&& GET_CODE (base = XEXP (base, 0)) == REG))
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&& REGNO_POINTER_ALIGN (REGNO (base)) >= 4)
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{
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rtx reg = gen_reg_rtx (SImode);
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rtx new_mem;
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if ((INTVAL (offset) & 2) == 2)
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{
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HOST_WIDE_INT new_offset = INTVAL (offset) ^ 2;
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new_mem = gen_rtx (MEM, SImode,
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plus_constant (base, new_offset));
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emit_insn (gen_movsi (reg, new_mem));
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}
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else
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{
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new_mem = gen_rtx (MEM, SImode,
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XEXP (operands[1], 0));
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emit_insn (gen_rotated_loadsi (reg, new_mem));
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}
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operands[1] = gen_lowpart (HImode, reg);
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}
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else
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{
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emit_insn (gen_movhi_bigend (operands[0], operands[1]));
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DONE;
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}
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}
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}
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}
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}
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}
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")
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(define_insn "rotated_loadsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o")
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(const_int 16)))]
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"! TARGET_SHORT_BY_BYTES"
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"*
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{
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rtx ops[2];
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ops[0] = operands[0];
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ops[1] = gen_rtx (MEM, SImode, plus_constant (XEXP (operands[1], 0), 2));
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output_asm_insn (\"ldr%?\\t%0, %1\\t%@ load-rotate\", ops);
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return \"\";
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}"
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[(set_attr "type" "load")])
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(define_expand "movhi_bytes"
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[(set (match_dup 2) (zero_extend:SI (mem:QI (match_operand:HI 1 "" ""))))
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(set (match_dup 3)
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