2420fff633
This changes the PowerPC64 --plt-align option to perform the usual alignment of code as suggested by its name, as well as the previous behaviour of padding so as to reduce boundary crossing. The old behaviour is had by using a negative parameter. The default is also changed to align plt stub code by default to 32 byte boundaries, the point being to get better bctr branch prediction on power8 and power9 hardware. bfd/ * elf64-ppp.c (plt_stub_pad): Handle positive and negative plt_stub_align. ld/ * ld.texinfo (--plt-align): Describe new behaviour of option. * emultempl/ppc64elf.em (params): Default plt_stub_align to 5. * testsuite/ld-powerpc/powerpc.exp: Pass --no-plt-align for selected tests. * testsuite/ld-powerpc/relbrlt.d: Pass --no-plt-align. * testsuite/ld-powerpc/elfv2so.d: Adjust expected output.
61 lines
1.8 KiB
Makefile
61 lines
1.8 KiB
Makefile
#source: relbrlt.s
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#as: -a64
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#ld: -melf64ppc --no-plt-align --no-ld-generated-unwind-info --emit-relocs
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#objdump: -Dr
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.*
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Disassembly of section \.text:
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0*100000c0 <_start>:
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[0-9a-f ]*: (49 bf 00 2d|2d 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: (49 bf 00 19|19 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: (49 bf 00 21|21 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: 00 00 00 00 \.long 0x0
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[0-9a-f ]*: (4b ff ff e4|e4 ff ff 4b) b .* <_start>
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\.\.\.
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: (e9 82 80 e8|e8 80 82 e9) ld r12,-32536\(r2\)
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[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00e8
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[0-9a-f ]*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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[0-9a-f ]*: (4e 80 04 20|20 04 80 4e) bctr
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[0-9a-f ]*<.*long_branch.*>:
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[0-9a-f ]*: (49 bf 00 10|10 00 bf 49) b .* <far>
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[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00fc
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: (e9 82 80 f0|f0 80 82 e9) ld r12,-32528\(r2\)
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[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00f0
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[0-9a-f ]*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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[0-9a-f ]*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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0*137e00fc <far>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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\.\.\.
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0*13bf00e0 <far2far>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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\.\.\.
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0*157e00e4 <huge>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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Disassembly of section \.branch_lt:
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0*157f00e8 .*:
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[0-9a-f ]*: (00 00 00 00|e0 00 bf 13) .*
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[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x13bf00e0
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[0-9a-f ]*: (13 bf 00 e0|00 00 00 00) .*
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[0-9a-f ]*: (00 00 00 00|e4 00 7e 15) .*
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[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x157e00e4
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[0-9a-f ]*: (15 7e 00 e4|00 00 00 00) .*
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