efd6b3591b
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
356 lines
11 KiB
Plaintext
356 lines
11 KiB
Plaintext
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
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Add new entries for VSCCLRM instruction.
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(print_insn_coprocessor): Handle new %C format control code.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (enum isa): New enum.
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(struct sopcode32): New structure.
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(coprocessor_opcodes): change type of entries to struct sopcode32 and
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set isa field of all current entries to ANY.
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(print_insn_coprocessor): Change type of insn to struct sopcode32.
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Only match an entry if its isa field allows the current mode.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
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CLRM.
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(print_insn_thumb32): Add logic to print %n CLRM register list.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %P
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and %Q patterns.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
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(print_insn_thumb32): Edit the switch case for %Z.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfl.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
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Arm register with r13 and r15 unpredictable.
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(thumb32_opcodes): New instructions for bfx and bflx.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instructions for bf.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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2019-04-12 John Darrington <john@darrington.wattle.id.au>
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s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
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"optr". ("operator" is a reserved word in c++).
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_print_operand): Add case for
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AARCH64_OPND_Rt_SP.
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(verify_constraints): Likewise.
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* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
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(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
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to accept Rt|SP as first operand.
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(AARCH64_OPERANDS): Add new Rt_SP.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
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2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
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* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Consolidate AVX512 BF16 entries.
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* i386-init.h: Regenerated.
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2019-04-07 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
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op_separator to control printing of spaces, comma and parens
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rather than need_comma, need_paren and spaces vars.
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2019-04-07 Alan Modra <amodra@gmail.com>
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PR 24421
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* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
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(print_insn_neon, print_insn_arm): Likewise.
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2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
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* i386-dis-evex.h (evex_table): Updated to support BF16
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instructions.
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* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
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and EVEX_W_0F3872_P_3.
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* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
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(cpu_flags): Add bitfield for CpuAVX512_BF16.
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* i386-opc.h (enum): Add CpuAVX512_BF16.
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(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
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* i386-opc.tbl: Add AVX512 BF16 instructions.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
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(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
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to favour printing of "-" branch hint when using the "y" bit.
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Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
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opcode until first operand is output.
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2019-04-04 Peter Bergner <bergner@linux.ibm.com>
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PR gas/24349
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* ppc-opc.c (valid_bo_pre_v2): Add comments.
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(valid_bo_post_v2): Add support for 'at' branch hints.
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(insert_bo): Only error on branch on ctr.
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(get_bo_hint_mask): New function.
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(insert_boe): Add new 'branch_taken' formal argument. Add support
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for inserting 'at' branch hints.
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(extract_boe): Add new 'branch_taken' formal argument. Add support
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for extracting 'at' branch hints.
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(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
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(BOE): Delete operand.
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(BOM, BOP): New operands.
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(RM): Update value.
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(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
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(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
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bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
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(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
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bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
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<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
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bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
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bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
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bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
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bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
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bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
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bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
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bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
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beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
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bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
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buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
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bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
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bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
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bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
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bttarl+>: New extended mnemonics.
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2019-03-28 Alan Modra <amodra@gmail.com>
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PR 24390
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* ppc-opc.c (BTF): Define.
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(powerpc_opcodes): Use for mtfsb*.
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* ppc-dis.c (print_insn_powerpc): Print fields with both
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PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
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(mapping_symbol_for_insn): Implement new algorithm.
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(print_insn): Remove duplicate code.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (print_insn_aarch64):
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Implement override.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
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order.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (last_stop_offset): New.
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(print_insn_aarch64): Use stop_offset.
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2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24359
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* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
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CPU_ANY_AVX2_FLAGS.
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* i386-init.h: Regenerated.
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2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24348
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* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
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vmovdqu16, vmovdqu32 and vmovdqu64.
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* i386-tbl.h: Regenerated.
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2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
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from vstrszb, vstrszh, and vstrszf.
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2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-opc.txt: Add instruction descriptions.
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2019-02-08 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
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<bne>: Likewise.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23212
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* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
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* aarch64-opc.c (verify_elem_sd): New.
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(fields): Add FLD_sz entr.
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* aarch64-tbl.h (_SIMD_INSN): New.
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(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
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fmulx scalar and vector by element isns.
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2019-02-07 Nick Clifton <nickc@redhat.com>
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* po/sv.po: Updated Swedish translation.
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2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-mkopc.c (main): Accept arch13 as cpu string.
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* s390-opc.c: Add new instruction formats and instruction opcode
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masks.
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* s390-opc.txt: Add new arch13 instructions.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (QL_LDST_AT): Update macro.
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(aarch64_opcode): Change encoding for stg, stzg
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st2g and st2zg.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
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* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
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* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
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* aarch64-dis.h (ext_addr_simple_2): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): Remove
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case for ldstgv_indexed.
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(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
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* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
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(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-01-23 Nick Clifton <nickc@redhat.com>
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* po/pt_BR.po: Updated Brazilian Portuguese translation.
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2019-01-21 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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* po/uk.po: Updated Ukranian translation.
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2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Fix typo in
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gs464, gs464e and gs264e descriptors.
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2019-01-19 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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* po/opcodes.pot: Regenerate.
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2018-06-24 Nick Clifton <nickc@redhat.com>
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2.32 branch created.
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2019-01-09 John Darrington <john@darrington.wattle.id.au>
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* s12z-dis.c (print_insn_s12z): Do not dereference an operand
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if it is null.
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-dis.c (opr_emit_disassembly): Do not omit an index if it is
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zero.
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2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
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* configure: Regenerate.
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2019-01-07 Alan Modra <amodra@gmail.com>
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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2019-01-03 John Darrington <john@darrington.wattle.id.au>
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* s12z-opc.c: New file.
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* s12z-opc.h: New file.
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* s12z-dis.c: Removed all code not directly related to display
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of instructions. Used the interface provided by the new files
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instead.
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* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
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* Makefile.in: Regenerate.
|
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* configure.ac (bfd_s12z_arch): Correct the dependencies.
|
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* configure: Regenerate.
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|
||
2019-01-01 Alan Modra <amodra@gmail.com>
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||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2018
|
||
|
||
Copyright (C) 2019 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|